fusesoc

What it is and what it does

FuseSoC is a build and package management system designed for hardware description languages like Verilog and VHDL. It abstracts away the differences between various HDL tools and simulators, allowing you to define hardware designs once and build or simulate them across multiple toolchains and FPGA targets without rewriting build scripts. The core problem it solves is IP reuse and design portability—instead of managing separate build configurations for each simulator or target, you describe your design in FuseSoC's core file format and let it handle tool invocation, dependency resolution, and parameter configuration.

FuseSoC is typically used in three contexts: managing libraries of reusable hardware IP cores, orchestrating builds and simulations in continuous integration pipelines, and porting existing designs to new FPGA boards or tool versions. It integrates with tools like Vivado, Quartus, and open-source simulators, and supports formal verification, linting, and SBOM generation. The package is production-stable, actively maintained, and widely used in both open-source hardware projects and commercial ASIC/FPGA development.

Use it for:

• Manage a library of reusable Verilog or VHDL IP cores and automatically resolve dependencies when building a larger design.
• Run regression tests on hardware designs against multiple simulators without manually switching tool configurations.
• Port an existing FPGA design to a new development board by updating target definitions rather than rewriting build scripts.
• Set up continuous integration for hardware projects to automatically build and simulate designs on every commit.
• Generate FPGA software bills of materials (SBOMs) through the spdxgen filter for compliance and documentation.
• Perform linting and formal verification on hardware code as part of an automated design flow.

Worth the install?

AI-flagged interpretation of the facts on this page — verify before relying

FuseSoC is a package manager and build abstraction tool for HDL code that enables reuse of IP cores, manages hardware designs, and coordinates builds and simulations across multiple tools and targets.

Yes. FuseSoC is a mature, actively maintained tool with no known vulnerabilities, low install friction, and permissive licensing. It is well-suited for anyone managing HDL projects, especially those needing to coordinate builds across multiple tools, reuse IP cores, or set up reproducible hardware build pipelines. Install it if you work with Verilog, VHDL, or SoC design; skip it if you only use a single closed-source tool with its own build system.

Install

fusesoc on PyPI

pip install fusesoc

uv add fusesoc

poetry add fusesoc

Installing fusesoc

Before you install

Low install friction with a pure Python wheel distribution and six straightforward runtime dependencies. The project is actively maintained with a recent commit history and has been in production use since 2016.

License in practice

Licensed under the permissive 2-clause BSD license, allowing free use, modification, and distribution for any project type without restriction.

Quickstart

pip install fusesoc
fusesoc library add fusesoc-cores https://github.com/fusesoc/fusesoc-cores
fusesoc core list
fusesoc run --target=sim i2c

Requires a supported HDL simulator (such as Icarus Verilog, ModelSim, or Xcelium) to be installed separately on the system to execute simulations.

Verify before relying

• Specific Python versions within the 3.6+ range that are most commonly tested or recommended by maintainers.
• Whether all six runtime dependencies are required for basic package management tasks or only for advanced features like simulation.
• Performance characteristics when managing large IP libraries or complex multi-target designs.

Package facts

Evidence: fusesoc-2.4.6-py3-none-any.whl

Keywords: VHDL, verilog, hdl, rtl, synthesis, FPGA, simulation, ASIC

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