tree-sitter-verilog
Verilog grammar for tree-sitter
Decision gist · record as of 2026-08-14
Yes, if you need to parse SystemVerilog code and are comfortable with a dormant but stable package. The permissive MIT license, zero runtime dependencies, and broad platform support make it low-risk. Install friction is medium due to compiled binaries, but prebuilt wheels for common platforms mitigate this. No known security vulnerabilities. Suitable for hardware design tooling, static analysis, and code generation workflows.AI-flagged interpretation of the facts on this page — verify before relying
Before you install
- Requires Python 3.9 or later; compiled binary wheels are platform-specific.
- Medium install friction due to compiled binary wheels; however, wheels are provided for common platforms (x86_64, ARM64, macOS, Linux, Windows).
- Package is dormant (last commit 2024-11-11, 642 days since release) but appears stable.
License · maintenance · safety
MIT (permissive) — MIT license is permissive; you can use, modify, and distribute this package with minimal restrictions, making it suitable for both open-source and commercial projects.
last release 2024-11-10 (642 days) · last repo commit 2024-11-11 · 123 stars
0 known vulnerabilities (OSV.dev, 2026-08-14) · 1,512,247 downloads/mo, #3,825 on PyPI
Alternatives
Verify before relying
pip install tree-sitter-verilog
import tree_sitter_verilog
# tree-sitter-verilog provides a SystemVerilog grammar for use with tree-sitter- How to instantiate and use the grammar with tree-sitter in Python (the package's public API).
- Whether the SystemVerilog grammar covers all language features or has known limitations.
- Performance characteristics for parsing large or complex Verilog files.
- Compatibility with specific tree-sitter versions or other Python ecosystem tools.
What it is and what it does
tree-sitter-verilog is a language grammar binding that integrates SystemVerilog parsing into the tree-sitter incremental parsing framework. It allows developers to parse Verilog and SystemVerilog code into abstract syntax trees, enabling static analysis, code generation, linting, and other language-aware tooling for hardware description languages.
The package ships as precompiled binaries for major platforms (macOS, Linux, Windows; x86_64 and ARM64 architectures), reducing installation friction. It has no runtime dependencies and requires Python 3.9 or later. The project is maintained by the tree-sitter community but is currently dormant, with the last commit in November 2024.
Use it for
- Build static analysis tools or linters that understand Verilog syntax and structure.
- Generate code from Verilog templates or perform automated refactoring on hardware designs.
- Implement IDE features like syntax highlighting or symbol navigation for Verilog.
- Parse and analyze Verilog test suites or design specifications programmatically.
- Integrate Verilog parsing into hardware verification or simulation workflows.
Worth the install?
AI-flagged interpretation of the facts on this page. Verify before relying on it.
Yes, if you need to parse SystemVerilog code and are comfortable with a dormant but stable package.
The permissive MIT license, zero runtime dependencies, and broad platform support make it low-risk. Install friction is medium due to compiled binaries, but prebuilt wheels for common platforms mitigate this. No known security vulnerabilities. Suitable for hardware design tooling, static analysis, and code generation workflows.
Install
tree-sitter-verilog on PyPI
Before you install
Medium install friction due to compiled binary wheels; however, wheels are provided for common platforms (x86_64, ARM64, macOS, Linux, Windows). Package is dormant (last commit 2024-11-11, 642 days since release) but appears stable.
Requires Python 3.9 or later; compiled binary wheels are platform-specific.
License in practice
MIT license is permissive; you can use, modify, and distribute this package with minimal restrictions, making it suitable for both open-source and commercial projects.
Quickstart
pip install tree-sitter-verilog
import tree_sitter_verilog
# tree-sitter-verilog provides a SystemVerilog grammar for use with tree-sitterVerify before relying
- How to instantiate and use the grammar with tree-sitter in Python (the package's public API).
- Whether the SystemVerilog grammar covers all language features or has known limitations.
- Performance characteristics for parsing large or complex Verilog files.
- Compatibility with specific tree-sitter versions or other Python ecosystem tools.
Package facts
| License | MIT permissive |
| Python support | Supports the current Python release >=3.9 |
| Install friction | Medium. Platform-specific wheel |
| Runtime dependencies | None |
| Maintenance | Dormant 642 days since the last release |
| Last repo commit | |
| First released | |
| Downloads | 1,512,247 / month, #3,825 on PyPI 30-day window, as of 2026-08-14 |
| Known vulnerabilities | None known OSV.dev, checked 2026-08-14 |
| Classifiers | Intended Audience :: DevelopersLicense :: OSI Approved :: MIT LicenseTopic :: Software Development :: CompilersTopic :: Text Processing :: LinguisticTyping :: Typed |
Evidence: tree_sitter_verilog-1.0.3-cp39-abi3-macosx_10_9_x86_64.whl; tree_sitter_verilog-1.0.3-cp39-abi3-macosx_11_0_arm64.whl; tree_sitter_verilog-1.0.3-cp39-abi3-manylinux_2_17_aarch64.manylinux2014_aarch64.whl; tree_sitter_verilog-1.0.3-cp39-abi3-manylinux_2_5_x86_64.manylinux1_x86_64.manylinux_2_17_x86_64.manylinux2014_x86_64.whl; tree_sitter_verilog-1.0.3-cp39-abi3-musllinux_1_2_x86_64.whl; tree_sitter_verilog-1.0.3-cp39-abi3-win_amd64.whl; tree_sitter_verilog-1.0.3-cp39-abi3-win_arm64.whl
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See also pyslang · tree-sitter-java · tree-sitter-go · tree-sitter-python · tree-sitter-c · svql · tree-sitter-json · tree-sitter-kotlin · tree-sitter-php · vcdvcd