---
id: tree-sitter-verilog
version: "1.0.3"
license: MIT
license_treatment: permissive
maintenance: dormant
---

# tree-sitter-verilog — Verilog grammar for tree-sitter

License: permissive · Maintenance: dormant · Downloads: 1.5M/mo

## What it is and what it does

tree-sitter-verilog is a language grammar binding that integrates SystemVerilog parsing into the tree-sitter incremental parsing framework. It allows developers to parse Verilog and SystemVerilog code into abstract syntax trees, enabling static analysis, code generation, linting, and other language-aware tooling for hardware description languages.

The package ships as precompiled binaries for major platforms (macOS, Linux, Windows; x86_64 and ARM64 architectures), reducing installation friction. It has no runtime dependencies and requires Python 3.9 or later. The project is maintained by the tree-sitter community but is currently dormant, with the last commit in November 2024.

Use it for:

- Build static analysis tools or linters that understand Verilog syntax and structure.
- Generate code from Verilog templates or perform automated refactoring on hardware designs.
- Implement IDE features like syntax highlighting or symbol navigation for Verilog.
- Parse and analyze Verilog test suites or design specifications programmatically.
- Integrate Verilog parsing into hardware verification or simulation workflows.

## Worth the install?

AI-flagged interpretation of the facts above — verify before relying.

Provides a SystemVerilog grammar parser for tree-sitter, enabling incremental parsing and syntax tree analysis of Verilog hardware description language code.

Yes, if you need to parse SystemVerilog code and are comfortable with a dormant but stable package. The permissive MIT license, zero runtime dependencies, and broad platform support make it low-risk. Install friction is medium due to compiled binaries, but prebuilt wheels for common platforms mitigate this. No known security vulnerabilities. Suitable for hardware design tooling, static analysis, and code generation workflows.

## Install

pip install tree-sitter-verilog
uv add tree-sitter-verilog
poetry add tree-sitter-verilog

## Installing tree-sitter-verilog

Before you install: Medium install friction due to compiled binary wheels; however, wheels are provided for common platforms (x86_64, ARM64, macOS, Linux, Windows). Package is dormant (last commit 2024-11-11, 642 days since release) but appears stable.

License in practice: MIT license is permissive; you can use, modify, and distribute this package with minimal restrictions, making it suitable for both open-source and commercial projects.

Quickstart:

pip install tree-sitter-verilog

import tree_sitter_verilog

# tree-sitter-verilog provides a SystemVerilog grammar for use with tree-sitter

Requires Python 3.9 or later; compiled binary wheels are platform-specific.

Verify before relying:

- How to instantiate and use the grammar with tree-sitter in Python (the package's public API).
- Whether the SystemVerilog grammar covers all language features or has known limitations.
- Performance characteristics for parsing large or complex Verilog files.
- Compatibility with specific tree-sitter versions or other Python ecosystem tools.

## Package facts

- License: MIT (permissive)
- Python support: supports_current
- Install friction: medium
- Maintenance: dormant
- Downloads: 1.5M/month (top 5,000 on PyPI)
- Known vulnerabilities: none known

## Tags

verilog parser, systemverilog grammar, tree-sitter verilog, hdl parsing, incremental verilog parsing, verilog syntax tree, hardware description language parser, verilog, hdl, parsing

[View on SkillFed](https://skillfed.io/packages/tree-sitter-verilog) · [View on PyPI](https://pypi.org/project/tree-sitter-verilog/)