peakrdl
Toolchain for control/status register automation and code generation.
Decision gist · record as of 2026-08-14
Yes. PeakRDL is a mature, actively maintained tool with low install friction and no security issues. It solves a real problem in hardware design—automating register generation and keeping hardware and software definitions synchronized. The copyleft license (LGPLv3) is standard for open-source EDA tools and poses no barrier for open-source or internal projects; commercial users should review license terms. Install it if your workflow involves SystemRDL or register automation.AI-flagged interpretation of the facts on this page — verify before relying
Before you install
- Requires Python 3.7 or later.
- The package is a compiler framework; actual code generation typically requires one or more of the plugin packages (peakrdl-systemrdl for Verilog, peakrdl-cheader for C, etc.).
- Low install friction; distributed as a pure Python wheel.
License · maintenance · safety
LGPLv3 (copyleft) — Licensed under LGPLv3 (copyleft). Derivative works and modifications must be released under the same license; static linking or bundling requires careful attention to license compliance. Suitable for open-source and internal projects, but commercial closed-source use requires legal review.
last release 2025-10-03 (315 days) · last repo commit 2026-07-14 · 208 stars
0 known vulnerabilities (OSV.dev, 2026-08-14) · 207,376 downloads/mo, #9,554 on PyPI
Alternatives
Verify before relying
pip install peakrdl
from peakrdl import RDLCompiler
compiler = RDLCompiler()
compiler.compile_file('registers.rdl')
root = compiler.elaborate()- Whether the 7 runtime dependencies are automatically installed or must be manually added based on desired output formats.
- Performance characteristics when processing large or complex register hierarchies.
- Community plugin ecosystem maturity and stability beyond the core plugins listed.
What it is and what it does
PeakRDL is a free, open-source toolchain for automating control and status register (CSR) generation in hardware and firmware projects. It reads SystemRDL 2.0 register descriptions—a domain-specific language for defining register layouts—and generates multiple artifacts: synthesizable SystemVerilog RTL register blocks, C register abstraction headers for software, HTML documentation, UVM register models for verification, and IP-XACT XML for interoperability. The tool is extensible via plugins, allowing teams to add custom code generators or integrate with their existing design flows.
The package is production-stable, actively maintained, and widely used in FPGA and ASIC design flows. It supports current Python versions (3.7+) and has no known security vulnerabilities. The core framework is lightweight and pure Python, making installation straightforward. Most users will pair it with one or more of the provided plugins (for Verilog generation, C headers, HTML docs, etc.) depending on their workflow needs.
Use it for
- Generate synthesizable Verilog register blocks from a single SystemRDL source, reducing manual RTL coding and synchronization errors.
- Produce C register abstraction headers automatically, keeping firmware and hardware register definitions in sync.
- Create rich HTML register documentation directly from register descriptions for design reviews and handoff.
- Import and export IP-XACT XML to integrate with other EDA tools and design flows.
- Build UVM register models for simulation-based verification without manual abstraction layer coding.
- Extend the toolchain with custom plugins to generate project-specific register artifacts or integrate with proprietary tools.
Worth the install?
AI-flagged interpretation of the facts on this page. Verify before relying on it.
Yes.
PeakRDL is a mature, actively maintained tool with low install friction and no security issues. It solves a real problem in hardware design—automating register generation and keeping hardware and software definitions synchronized. The copyleft license (LGPLv3) is standard for open-source EDA tools and poses no barrier for open-source or internal projects; commercial users should review license terms. Install it if your workflow involves SystemRDL or register automation.
Install
peakrdl on PyPI
Before you install
Low install friction; distributed as a pure Python wheel. Maintained actively with a recent release and ongoing repository commits. Depends on 7 runtime plugins (peakrdl-cli, peakrdl-html, peakrdl-ipxact, peakrdl-regblock, peakrdl-systemrdl, peakrdl-uvm, peakrdl-cheader), all of which are part of the same ecosystem.
Requires Python 3.7 or later. The package is a compiler framework; actual code generation typically requires one or more of the plugin packages (peakrdl-systemrdl for Verilog, peakrdl-cheader for C, etc.).
License in practice
Licensed under LGPLv3 (copyleft). Derivative works and modifications must be released under the same license; static linking or bundling requires careful attention to license compliance. Suitable for open-source and internal projects, but commercial closed-source use requires legal review.
Quickstart
pip install peakrdl
from peakrdl import RDLCompiler
compiler = RDLCompiler()
compiler.compile_file('registers.rdl')
root = compiler.elaborate()
Verify before relying
- Whether the 7 runtime dependencies are automatically installed or must be manually added based on desired output formats.
- Performance characteristics when processing large or complex register hierarchies.
- Community plugin ecosystem maturity and stability beyond the core plugins listed.
Package facts
| License | LGPLv3 copyleft |
| Python support | Supports the current Python release >=3.7 |
| Install friction | Low. Pure-Python wheel |
| Runtime dependencies | 7 packagespeakrdl-clipeakrdl-htmlpeakrdl-ipxactpeakrdl-regblockpeakrdl-systemrdlpeakrdl-uvmpeakrdl-cheader |
| Maintenance | Actively maintained 315 days since the last release |
| Last repo commit | |
| First released | |
| Downloads | 207,376 / month, #9,554 on PyPI 30-day window, as of 2026-08-14 |
| Known vulnerabilities | None known OSV.dev, checked 2026-08-14 |
| Classifiers | Development Status :: 5 - Production/StableIntended Audience :: DevelopersLicense :: OSI Approved :: GNU Lesser General Public License v3 (LGPLv3)Operating System :: OS IndependentProgramming Language :: PythonProgramming Language :: Python :: 3Programming Language :: Python :: 3 :: OnlyTopic :: Scientific/Engineering :: Electronic Design Automation (EDA) |
Evidence: peakrdl-1.5.0-py3-none-any.whl
Tags
Let your AI agent find packages like this
Example. Real query, live index.
You found this page by searching. An agent finds it by wishing: SkillFed indexes 14,416 PyPI packages by what they can do, searchable in plain language.
wish › “CSR automation”
- peakrdlPeakRDL is a control and status register (CSR) generator toolchain…
- peakrdl-cliPeakRDL is a command-line tool that generates register abstraction…
- peakrdl-ipxactConverts between SystemRDL register descriptions and IP-XACT XML…
Give your agent the search over MCP, or paste the wish link into any chat.
More Electronic Design Automation (EDA) packages
Parses and elaborates SystemRDL 2.0 register description language into a traversable register model, enabling custom code generation for hardware register spaces.
Install it if you need to parse SystemRDL files or build custom register generators.
Tests whether a graph is planar, computes planar embeddings, draws planar graphs as ASCII art, and isolates forbidden subgraphs using algorithms from the Edge Addition Planarity Suite.
cocotb is a Python framework for writing testbenches that simulate and verify VHDL and Verilog hardware designs through coroutine-based cosimulation.
pyslang provides Python bindings to parse, analyze, and elaborate SystemVerilog code, exposing the underlying slang compiler's syntax tree and evaluation capabilities for programmatic inspection and manipulation.
Converts between SystemRDL register descriptions and IP-XACT XML format, enabling import and export workflows for hardware register modeling.
KLayout is a Python package for layout viewing, editing, and scripting in electronic design automation (EDA) workflows, providing programmatic access to design manipulation and analysis.
See also peakrdl-cli · peakrdl-regblock · peakrdl-systemrdl · peakrdl-uvm · peakrdl-python · peakrdl-cheader · peakrdl-html · fusesoc