peakrdl

What it is and what it does

PeakRDL is a free, open-source toolchain for automating control and status register (CSR) generation in hardware and firmware projects. It reads SystemRDL 2.0 register descriptions—a domain-specific language for defining register layouts—and generates multiple artifacts: synthesizable SystemVerilog RTL register blocks, C register abstraction headers for software, HTML documentation, UVM register models for verification, and IP-XACT XML for interoperability. The tool is extensible via plugins, allowing teams to add custom code generators or integrate with their existing design flows.

The package is production-stable, actively maintained, and widely used in FPGA and ASIC design flows. It supports current Python versions (3.7+) and has no known security vulnerabilities. The core framework is lightweight and pure Python, making installation straightforward. Most users will pair it with one or more of the provided plugins (for Verilog generation, C headers, HTML docs, etc.) depending on their workflow needs.

Use it for:

• Generate synthesizable Verilog register blocks from a single SystemRDL source, reducing manual RTL coding and synchronization errors.
• Produce C register abstraction headers automatically, keeping firmware and hardware register definitions in sync.
• Create rich HTML register documentation directly from register descriptions for design reviews and handoff.
• Import and export IP-XACT XML to integrate with other EDA tools and design flows.
• Build UVM register models for simulation-based verification without manual abstraction layer coding.
• Extend the toolchain with custom plugins to generate project-specific register artifacts or integrate with proprietary tools.

Worth the install?

AI-flagged interpretation of the facts on this page — verify before relying

PeakRDL is a control and status register (CSR) generator toolchain that processes SystemRDL register descriptions and generates synthesizable SystemVerilog RTL, C register headers, HTML documentation, UVM models, and IP-XACT exports.

Yes. PeakRDL is a mature, actively maintained tool with low install friction and no security issues. It solves a real problem in hardware design—automating register generation and keeping hardware and software definitions synchronized. The copyleft license (LGPLv3) is standard for open-source EDA tools and poses no barrier for open-source or internal projects; commercial users should review license terms. Install it if your workflow involves SystemRDL or register automation.

Install

peakrdl on PyPI

pip install peakrdl

uv add peakrdl

poetry add peakrdl

Installing peakrdl

Before you install

Low install friction; distributed as a pure Python wheel. Maintained actively with a recent release and ongoing repository commits. Depends on 7 runtime plugins (peakrdl-cli, peakrdl-html, peakrdl-ipxact, peakrdl-regblock, peakrdl-systemrdl, peakrdl-uvm, peakrdl-cheader), all of which are part of the same ecosystem.

License in practice

Licensed under LGPLv3 (copyleft). Derivative works and modifications must be released under the same license; static linking or bundling requires careful attention to license compliance. Suitable for open-source and internal projects, but commercial closed-source use requires legal review.

Quickstart

pip install peakrdl

from peakrdl import RDLCompiler

compiler = RDLCompiler()
compiler.compile_file('registers.rdl')
root = compiler.elaborate()

Requires Python 3.7 or later. The package is a compiler framework; actual code generation typically requires one or more of the plugin packages (peakrdl-systemrdl for Verilog, peakrdl-cheader for C, etc.).

Verify before relying

• Whether the 7 runtime dependencies are automatically installed or must be manually added based on desired output formats.
• Performance characteristics when processing large or complex register hierarchies.
• Community plugin ecosystem maturity and stability beyond the core plugins listed.

Package facts

Evidence: peakrdl-1.5.0-py3-none-any.whl

Keywords: SystemRDL, PeakRDL, CSR, compiler, tool, registers, generator, C, header, software, Verilog, SystemVerilog, register abstraction layer, FPGA, ASIC

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