peakrdl-cli
Command-line tool for control/status register automation and code generation.
Decision gist · record as of 2026-08-14
Yes. PeakRDL is production-stable, actively maintained, has low install friction, and solves a real problem in hardware-firmware co-design by automating register code generation from a single source. The copyleft license is a consideration only if you plan to modify and redistribute the tool itself. For teams working with SystemRDL or IP-XACT, it's a worthwhile addition to the build toolchain.AI-flagged interpretation of the facts on this page — verify before relying
Before you install
- Requires Python 3.7 or later.
- SystemRDL input files must be valid SystemRDL 2.0 format.
- Low friction install with only two runtime dependencies (systemrdl-compiler and tomli).
License · maintenance · safety
LGPLv3 (copyleft) — Licensed under LGPLv3 (copyleft). Any derivative work or modification must be distributed under the same license; proprietary use of modified versions requires compliance with copyleft obligations.
last release 2025-10-03 (315 days) · last repo commit 2026-07-14 · 208 stars
0 known vulnerabilities (OSV.dev, 2026-08-14) · 101,129 downloads/mo, #12,961 on PyPI
Alternatives
Verify before relying
pip install peakrdl-cli
peakrdl generate -o output/ register_spec.rdl- Whether the tool's plugin system is documented well enough for custom extensions
- Performance characteristics when processing large register specifications
- Completeness of IP-XACT import/export support relative to the standard
What it is and what it does
PeakRDL is a register automation toolchain that reads SystemRDL register descriptions and generates multiple artifacts: synthesizable SystemVerilog RTL blocks, C register abstraction headers for firmware, HTML documentation, and UVM register models. It also supports importing and exporting IP-XACT XML, making it a bridge between register specification formats. The tool is centered on SystemRDL 2.0 but can work with other CSR specifications.
For hardware and firmware teams, PeakRDL eliminates manual register definition and code generation by automating the flow from a single source-of-truth register description to both hardware (Verilog) and software (C) artifacts. It's designed for FPGA and ASIC projects where register consistency between RTL and firmware is critical. The package includes extensibility through plugins, allowing teams to add custom generators for their specific workflows.
Use it for
- Generate matching Verilog RTL and C headers from a single SystemRDL register specification to keep hardware and firmware in sync
- Convert between SystemRDL and IP-XACT formats for integration with existing design flows and tools
- Create automated HTML documentation of register maps for design reviews and firmware integration
- Build UVM register models for testbench verification from the same register description
- Extend the tool with custom code generators via plugins for project-specific register handling
Worth the install?
AI-flagged interpretation of the facts on this page. Verify before relying on it.
Yes.
PeakRDL is production-stable, actively maintained, has low install friction, and solves a real problem in hardware-firmware co-design by automating register code generation from a single source. The copyleft license is a consideration only if you plan to modify and redistribute the tool itself. For teams working with SystemRDL or IP-XACT, it's a worthwhile addition to the build toolchain.
Install
peakrdl-cli on PyPI
Before you install
Low friction install with only two runtime dependencies (systemrdl-compiler and tomli). The package is actively maintained with recent commits and has been in production-stable status since its first release.
Requires Python 3.7 or later. SystemRDL input files must be valid SystemRDL 2.0 format.
License in practice
Licensed under LGPLv3 (copyleft). Any derivative work or modification must be distributed under the same license; proprietary use of modified versions requires compliance with copyleft obligations.
Quickstart
pip install peakrdl-cli
peakrdl generate -o output/ register_spec.rdl
Verify before relying
- Whether the tool's plugin system is documented well enough for custom extensions
- Performance characteristics when processing large register specifications
- Completeness of IP-XACT import/export support relative to the standard
Package facts
| License | LGPLv3 copyleft |
| Python support | Supports the current Python release >=3.7 |
| Install friction | Low. Pure-Python wheel |
| Runtime dependencies | 2 packagessystemrdl-compilertomli |
| Maintenance | Actively maintained 315 days since the last release |
| Last repo commit | |
| First released | |
| Downloads | 101,129 / month, #12,961 on PyPI 30-day window, as of 2026-08-14 |
| Known vulnerabilities | None known OSV.dev, checked 2026-08-14 |
| Classifiers | Development Status :: 5 - Production/StableIntended Audience :: DevelopersLicense :: OSI Approved :: GNU Lesser General Public License v3 (LGPLv3)Operating System :: OS IndependentProgramming Language :: PythonProgramming Language :: Python :: 3Programming Language :: Python :: 3 :: OnlyTopic :: Scientific/Engineering :: Electronic Design Automation (EDA) |
Evidence: peakrdl_cli-1.5.0-py3-none-any.whl
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See also peakrdl · peakrdl-regblock · peakrdl-uvm · peakrdl-python · peakrdl-html · peakrdl-cheader · peakrdl-systemrdl · fusesoc