peakrdl-regblock

What it is and what it does

PeakRDL-regblock is a compiler that transforms SystemRDL register descriptions into synthesizable SystemVerilog code for control/status register blocks. It sits in the hardware design toolchain as a code generator, taking a high-level register abstraction language (SystemRDL) and producing low-level Verilog suitable for FPGA and ASIC projects. The tool depends on systemrdl-compiler for parsing and validation, and uses Jinja2 for template-based code generation.

It is designed for hardware engineers and RTL developers who want to specify register layouts declaratively in SystemRDL rather than hand-coding repetitive Verilog. The package is actively maintained, marked as production-stable, and carries a copyleft license that requires derivative works to remain open-source.

Use it for:

• Generate CSR blocks for FPGA designs from a single SystemRDL specification to reduce hand-coding and ensure consistency.
• Automate register documentation and validation by compiling a formal register abstraction layer into synthesizable Verilog.
• Integrate register generation into hardware build pipelines alongside other EDA tools for ASIC and FPGA projects.
• Create reusable register templates across multiple design projects using SystemRDL as a portable register definition format.

Worth the install?

AI-flagged interpretation of the facts on this page — verify before relying

Compiles SystemRDL register descriptions into synthesizable SystemVerilog control/status register (CSR) blocks for hardware design.

Yes, if you work with SystemRDL register descriptions in FPGA or ASIC design. Low install friction, active maintenance, no known vulnerabilities, and production-stable status make it reliable. The copyleft license is a constraint only if your project must remain proprietary; open-source hardware projects face no barrier.

Install

peakrdl-regblock on PyPI

pip install peakrdl-regblock

uv add peakrdl-regblock

poetry add peakrdl-regblock

Installing peakrdl-regblock

Before you install

Low friction installation with only two runtime dependencies (systemrdl-compiler and Jinja2). Active maintenance with recent release and 84 repository stars indicates ongoing support.

License in practice

LGPLv3 copyleft license requires derivative works to remain open-source and include license notices; suitable for open-source projects but may conflict with proprietary hardware design workflows.

Quickstart

pip install peakrdl-regblock

from peakrdl.compiler import RDLCompiler
from peakrdl_regblock import RegBlockExporter

compiler = RDLCompiler()
compiler.compile_file('design.rdl')
root = compiler.elaborate()
exporter = RegBlockExporter()
exporter.export(root, 'output.sv')

Requires systemrdl-compiler as a runtime dependency; assumes an existing SystemRDL design file (.rdl) as input.

Verify before relying

• Whether the generated SystemVerilog output requires post-processing or is directly synthesizable by standard tools.
• Support scope for SystemRDL specification versions and which Verilog/SystemVerilog standards are targeted.
• Integration points with common EDA tools (Vivado, Quartus, etc.) beyond raw code generation.

Package facts

Evidence: peakrdl_regblock-1.3.1-py3-none-any.whl

Keywords: SystemRDL, PeakRDL, CSR, compiler, tool, registers, generator, Verilog, SystemVerilog, register abstraction layer, FPGA, ASIC

Tags

More Electronic Design Automation (EDA) packages

Further reading