peakrdl-regblock
Compile SystemRDL into a SystemVerilog control/status register (CSR) block
Decision gist · record as of 2026-08-14
Yes, if you work with SystemRDL register descriptions in FPGA or ASIC design. Low install friction, active maintenance, no known vulnerabilities, and production-stable status make it reliable. The copyleft license is a constraint only if your project must remain proprietary; open-source hardware projects face no barrier.AI-flagged interpretation of the facts on this page — verify before relying
Before you install
- Requires systemrdl-compiler as a runtime dependency; assumes an existing SystemRDL design file (.rdl) as input.
- Low friction installation with only two runtime dependencies (systemrdl-compiler and Jinja2).
- Active maintenance with recent release and 84 repository stars indicates ongoing support.
License · maintenance · safety
LGPLv3 (copyleft) — LGPLv3 copyleft license requires derivative works to remain open-source and include license notices; suitable for open-source projects but may conflict with proprietary hardware design workflows.
last release 2026-03-28 (139 days) · last repo commit 2026-03-28 · 84 stars
0 known vulnerabilities (OSV.dev, 2026-08-14) · 222,534 downloads/mo, #9,262 on PyPI
Alternatives
Verify before relying
pip install peakrdl-regblock
from peakrdl.compiler import RDLCompiler
from peakrdl_regblock import RegBlockExporter
compiler = RDLCompiler()
compiler.compile_file('design.rdl')
root = compiler.elaborate()
exporter = RegBlockExporter()
exporter.export(root, 'output.sv')- Whether the generated SystemVerilog output requires post-processing or is directly synthesizable by standard tools.
- Support scope for SystemRDL specification versions and which Verilog/SystemVerilog standards are targeted.
- Integration points with common EDA tools (Vivado, Quartus, etc.) beyond raw code generation.
What it is and what it does
PeakRDL-regblock is a compiler that transforms SystemRDL register descriptions into synthesizable SystemVerilog code for control/status register blocks. It sits in the hardware design toolchain as a code generator, taking a high-level register abstraction language (SystemRDL) and producing low-level Verilog suitable for FPGA and ASIC projects. The tool depends on systemrdl-compiler for parsing and validation, and uses Jinja2 for template-based code generation.
It is designed for hardware engineers and RTL developers who want to specify register layouts declaratively in SystemRDL rather than hand-coding repetitive Verilog. The package is actively maintained, marked as production-stable, and carries a copyleft license that requires derivative works to remain open-source.
Use it for
- Generate CSR blocks for FPGA designs from a single SystemRDL specification to reduce hand-coding and ensure consistency.
- Automate register documentation and validation by compiling a formal register abstraction layer into synthesizable Verilog.
- Integrate register generation into hardware build pipelines alongside other EDA tools for ASIC and FPGA projects.
- Create reusable register templates across multiple design projects using SystemRDL as a portable register definition format.
Worth the install?
AI-flagged interpretation of the facts on this page. Verify before relying on it.
Yes, if you work with SystemRDL register descriptions in FPGA or ASIC design.
Low install friction, active maintenance, no known vulnerabilities, and production-stable status make it reliable. The copyleft license is a constraint only if your project must remain proprietary; open-source hardware projects face no barrier.
Install
peakrdl-regblock on PyPI
Before you install
Low friction installation with only two runtime dependencies (systemrdl-compiler and Jinja2). Active maintenance with recent release and 84 repository stars indicates ongoing support.
Requires systemrdl-compiler as a runtime dependency; assumes an existing SystemRDL design file (.rdl) as input.
License in practice
LGPLv3 copyleft license requires derivative works to remain open-source and include license notices; suitable for open-source projects but may conflict with proprietary hardware design workflows.
Quickstart
pip install peakrdl-regblock
from peakrdl.compiler import RDLCompiler
from peakrdl_regblock import RegBlockExporter
compiler = RDLCompiler()
compiler.compile_file('design.rdl')
root = compiler.elaborate()
exporter = RegBlockExporter()
exporter.export(root, 'output.sv')Verify before relying
- Whether the generated SystemVerilog output requires post-processing or is directly synthesizable by standard tools.
- Support scope for SystemRDL specification versions and which Verilog/SystemVerilog standards are targeted.
- Integration points with common EDA tools (Vivado, Quartus, etc.) beyond raw code generation.
Package facts
| License | LGPLv3 copyleft |
| Python support | Supports the current Python release >=3.7 |
| Install friction | Low. Pure-Python wheel |
| Runtime dependencies | 2 packagessystemrdl-compilerJinja2 |
| Maintenance | Actively maintained 139 days since the last release |
| Last repo commit | |
| First released | |
| Downloads | 222,534 / month, #9,262 on PyPI 30-day window, as of 2026-08-14 |
| Known vulnerabilities | None known OSV.dev, checked 2026-08-14 |
| Classifiers | Development Status :: 5 - Production/StableIntended Audience :: DevelopersLicense :: OSI Approved :: GNU Lesser General Public License v3 (LGPLv3)Operating System :: OS IndependentProgramming Language :: PythonProgramming Language :: Python :: 3Programming Language :: Python :: 3 :: OnlyTopic :: Scientific/Engineering :: Electronic Design Automation (EDA) |
Evidence: peakrdl_regblock-1.3.1-py3-none-any.whl
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See also fusesoc · peakrdl · peakrdl-cli · peakrdl-python · peakrdl-cheader · peakrdl-systemrdl · svql · peakrdl-uvm · peakrdl-html