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0.000 to 0.805: a 42-skill library rescues a model that can't solve a single hard RTL problem alone

Notes on LEGO: An LLM Skill-Based Front-End Design Generation Platform (arXiv:2604.23355) — Jincheng Lou, Ruohang Xu, Jie Ma, Runzhe Tao, Xinyu Qu, Yibo Lin · April 2026

Note published · written by SkillFed’s research pipeline from the paper above · how these notes are made

AI-assisted notes · reviewed by SkillFed Skill retrieval

LEGO breaks the digital front-end chip-design flow — spec generation, RTL coding, testbench generation, simulation, debug — into six fixed steps and represents every reusable capability within those steps as a circuit skill: a seven-field unit (name, function, constraints, entry command, IO spec, schema, completion criteria) that any code agent can invoke like a subroutine. An automated three-stage pipeline builds the library from there — summarize capabilities, map to a workflow step, standardize the fields — mining more than 100 papers and 11 open-source EDA-agent projects (VerilogCoder, MAGE, Spec2RTL-Agent, AutoBench, the hierarchy-verilog line of work, RTLFixer, and others) down to 42 skills across 24 functional groups. A companion retrieval layer, Agent Skill RAG, skips embedding models entirely: it loads only short skill descriptions up front and pulls the full entry — symptom, root cause, fix — once a match is found, keeping lookup at sub-millisecond speed while letting new fixes get appended as plain text.

The test: VerilogEval v2's 156 specification-to-RTL tasks, run end to end through gpt-5.2-codex at its highest ('extra-high') reasoning setting, filtered down to the 41 problems the model failed outright — a hard 0.000 Pass@1 floor. Handing that same model a single RTL-generation skill lifts Pass@1 to 0.56–0.61; adding a debugging skill with a retry loop pushes it to 0.805, 33 of 41 solved, an 80.5-point swing from zero. Cross-project skill composition does just as well: a pipeline built from a hierarchy-style spec skill, a hierarchical RTL generator, and an RTLFixer-derived repair skill also reaches 0.805 — beating the hierarchy-verilog baseline by 14.6 points and VerilogCoder by 2.5, tying MAGE, and beating standalone RTLFixer by 39 points.

Key numbers

Circuit skills in the library42 (11 open-source projects, 24 functional groups)
Baseline Pass@1 (gpt-5.2-codex, xhigh, hard subset)0.000 (0/41 solved)
Best single/composed skill result0.805 (33/41 solved, +80.5 pts vs baseline)
Gain vs hierarchy-verilog / VerilogCoder baselines+14.6 pts / +2.5 pts (ties MAGE)
Agent Skill RAG retrieval speedsub-millisecond, no embedding model

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References

  1. LEGO: An LLM Skill-Based Front-End Design Generation Platform — Lou, Xu, Ma, Tao, Qu & Lin, arXiv:2604.23355 (2026)
  2. MAGE: A Multi-Agent Engine for Automated RTL Code Generation — Zhao et al., DAC 2025
  3. VerilogCoder: Autonomous Verilog Coding Agents with Graph-Based Planning and AST-Based Waveform Tracing — Ho, Ren & Khailany, AAAI 2025
  4. HiVeGen: Hierarchical LLM-Based Verilog Generation for Scalable Chip Design (the hierarchy-verilog baseline) — Tang et al., ICLAD 2025
  5. RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models — Tsai, Liu & Ren, DAC 2024