{"categories":[{"label":"Electronic Design Automation (EDA)","url":"https://skillfed.io/packages/category/scientific-engineering-electronic-design-automation-eda"}],"enrichment":{"capability":"Compiles SystemRDL register descriptions into synthesizable SystemVerilog control/status register (CSR) blocks for hardware design.","skillfed_tags":["hardware-design","code-generation","eda-tools"],"use_cases":["Generate CSR blocks for FPGA designs from a single SystemRDL specification to reduce hand-coding and ensure consistency.","Automate register documentation and validation by compiling a formal register abstraction layer into synthesizable Verilog.","Integrate register generation into hardware build pipelines alongside other EDA tools for ASIC and FPGA projects.","Create reusable register templates across multiple design projects using SystemRDL as a portable register definition format."],"what_it_does":"PeakRDL-regblock is a compiler that transforms SystemRDL register descriptions into synthesizable SystemVerilog code for control/status register blocks. It sits in the hardware design toolchain as a code generator, taking a high-level register abstraction language (SystemRDL) and producing low-level Verilog suitable for FPGA and ASIC projects. The tool depends on systemrdl-compiler for parsing and validation, and uses Jinja2 for template-based code generation.\n\nIt is designed for hardware engineers and RTL developers who want to specify register layouts declaratively in SystemRDL rather than hand-coding repetitive Verilog. The package is actively maintained, marked as production-stable, and carries a copyleft license that requires derivative works to remain open-source.","worth_installing":"Yes, if you work with SystemRDL register descriptions in FPGA or ASIC design. Low install friction, active maintenance, no known vulnerabilities, and production-stable status make it reliable. The copyleft license is a constraint only if your project must remain proprietary; open-source hardware projects face no barrier."},"id":"peakrdl-regblock","links":{"html":"https://skillfed.io/packages/peakrdl-regblock","md":"https://skillfed.io/packages/peakrdl-regblock.md","pypi":"https://pypi.org/project/peakrdl-regblock/"},"maintenance":{"status":"active"},"meta":{"latest_release":"2026-03-28","license_spdx":null,"license_treatment":"copyleft","name":"peakrdl-regblock","python_support":"supports_current","summary":"Compile SystemRDL into a SystemVerilog control/status register (CSR) block"},"popularity":{"monthly_downloads":222534,"position":9262,"tier":"top_15000"},"security":{"n_vulnerabilities":0},"version":"1.3.1"}