Packages
Parses and elaborates SystemRDL 2.0 register description language into a traversable register model, enabling custom code generation for hardware register spaces.
Install it if you need to parse SystemRDL files or build custom register generators.
Tests whether a graph is planar, computes planar embeddings, draws planar graphs as ASCII art, and isolates forbidden subgraphs using algorithms from the Edge Addition Planarity Suite.
cocotb is a Python framework for writing testbenches that simulate and verify VHDL and Verilog hardware designs through coroutine-based cosimulation.
pyslang provides Python bindings to parse, analyze, and elaborate SystemVerilog code, exposing the underlying slang compiler's syntax tree and evaluation capabilities for programmatic inspection and manipulation.
Converts between SystemRDL register descriptions and IP-XACT XML format, enabling import and export workflows for hardware register modeling.
KLayout is a Python package for layout viewing, editing, and scripting in electronic design automation (EDA) workflows, providing programmatic access to design manipulation and analysis.
Adds constrained randomization and functional coverage capabilities to cocotb, enabling SystemVerilog-style verification methodologies in Python for hardware testbenches.
Implements the IEEE 1800.2 Universal Verification Methodology (UVM) standard in Python, enabling RTL verification testbenches to run through cocotb simulators.
Install it if your team prefers Python over SystemVerilog or if you are building testbenches for projects already using cocotb.
Exports a compiled register model into SystemRDL code, enabling conversion from other file formats like IP-XACT to SystemRDL representation.
cocotb-test wraps cocotb hardware simulations in pytest, letting you write and run HDL testbenches as standard Python unit tests without Makefiles.
Generates C header files from SystemRDL register models, converting hardware register specifications into C code suitable for software development.
Install it if you work with SystemRDL register models and need C headers.
Compiles SystemRDL register descriptions into synthesizable SystemVerilog control/status register (CSR) blocks for hardware design.
Edalize abstracts the interface to EDA tools (simulators, synthesis tools, linters) so you can define a project once and run it across different tools without rewriting tool-specific configurations.
Gdstk is a Python module for creating and manipulating GDSII and OASIS files, with support for boolean operations, polygon offsetting, and point-in-polygon queries for CAD layout design.
PeakRDL is a control and status register (CSR) generator toolchain that processes SystemRDL register descriptions and generates synthesizable SystemVerilog RTL, C register headers, HTML documentation, UVM models, and IP-XACT exports.
Install it if your workflow involves SystemRDL or register automation.
Generates HTML documentation for register address spaces from compiled SystemRDL register descriptions, converting hardware register models into browsable web documentation.
Install it if you work with SystemRDL register models and need to generate documentation.
PyVCD writes and reads Value Change Dump (VCD) files as specified in IEEE 1800-2023, enabling capture and analysis of signal changes over time in digital simulations.
Install it if you need to generate or consume VCD waveform files in Python.
Generates UVM (Universal Verification Methodology) register models in SystemVerilog from compiled SystemRDL register descriptions, enabling automated hardware verification testbench creation.
SiliconCompiler is a modular hardware build system that automates translation from source code (RTL, Chisel, MLIR, etc.) to silicon through a programmable Python API, supporting ASIC, FPGA, simulation, and linting workflows.
Install it if you need to automate hardware design flows, integrate RTL-to-GDS into CI/CD, or explore ASIC/FPGA design without managing many EDA tools separately.
Verifies whether two quantum circuits are functionally equivalent using decision-diagram construction, simulation-based falsification, ZX-calculus rewriting, and automated checking flows to prove equivalence or find counterexamples.
Install it if you need to verify quantum circuit equivalence, validate compilation flows, or test parameterized quantum algorithms.
Generates a Python Register Access Layer (RAL) from SystemRDL specifications, enabling programmatic access to hardware registers through Python classes and a built-in simulator.
PeakRDL is a command-line tool that generates register abstraction code and documentation from SystemRDL register descriptions, producing synthesizable SystemVerilog RTL, C headers, HTML docs, and UVM models.
PyAEDT provides a Python API to script and automate Ansys Electronics Desktop (AEDT), including its 3D solvers (HFSS, Maxwell, Icepak, Q3D), 2D tools, circuit simulators, and layout tools.