pyuvm
A Python implementation of the UVM using cocotb
Decision gist · record as of 2026-08-14
Yes. pyuvm is actively maintained, has no known vulnerabilities, installs with low friction, and is permissively licensed. It is the right choice if you need UVM-compliant verification in Python and have access to a cocotb-compatible simulator. Install it if your team prefers Python over SystemVerilog or if you are building testbenches for projects already using cocotb.AI-flagged interpretation of the facts on this page — verify before relying
Before you install
- Requires a hardware simulator (e.g., Icarus, VCS, Vivado) and cocotb to be configured; simulation runs through Makefiles that invoke cocotb-config.
- Low friction installation via pip; cocotb is automatically installed as a dependency.
- The package is actively maintained with recent commits and a stable release history since 2020.
License · maintenance · safety
permissive license (permissive) — Licensed under Apache Software License (permissive), allowing commercial and private use with minimal restrictions.
last release 2025-10-18 (300 days) · last repo commit 2026-08-10 · 567 stars
0 known vulnerabilities (OSV.dev, 2026-08-14) · 362,935 downloads/mo, #7,228 on PyPI
Alternatives
Verify before relying
pip install pyuvm
from pyuvm import *
my_object = uvm_object("my_object")
print("object name:", my_object.get_name())- Whether all IEEE 1800.2 sections beyond those listed (e.g., Memory, Backdoor access) are planned or out of scope.
- Performance characteristics when running large-scale testbenches compared to SystemVerilog UVM.
- Compatibility matrix with specific simulator versions and cocotb releases.
What it is and what it does
pyuvm brings the industry-standard Universal Verification Methodology to Python, implementing the IEEE 1800.2 standard without requiring SystemVerilog. It provides core UVM abstractions—base classes, factory, phasing, transaction-level modeling (TLM), components, sequences, and a register access layer—all designed to work with cocotb to drive hardware simulations. Python's object-oriented features (multiple inheritance, no strict typing, no parameterized classes) make UVM testbench code simpler to write and maintain than the SystemVerilog equivalent.
The package covers the most-used sections of IEEE 1800.2, including base classes, reporting, factory, phasing, TLM interfaces, component hierarchy, sequences, and register blocks. Some advanced features like Memory and atomic Backdoor access remain unimplemented. Testbenches import pyuvm and use cocotb coroutines to interact with simulators, schedule events, and verify RTL designs through reusable, standardized testbench components.
Use it for
- Build reusable RTL verification testbenches in Python that follow IEEE 1800.2 conventions without learning SystemVerilog.
- Verify hardware designs (Verilog or VHDL) using transaction-level modeling and UVM sequences in a Python environment.
- Develop register verification tests using the register access layer to model and test memory-mapped hardware registers.
- Create portable testbenches that can run across different simulators by leveraging cocotb's simulator abstraction.
- Teach verification methodology to engineers familiar with Python but new to SystemVerilog UVM.
Worth the install?
AI-flagged interpretation of the facts on this page. Verify before relying on it.
Yes.
pyuvm is actively maintained, has no known vulnerabilities, installs with low friction, and is permissively licensed. It is the right choice if you need UVM-compliant verification in Python and have access to a cocotb-compatible simulator. Install it if your team prefers Python over SystemVerilog or if you are building testbenches for projects already using cocotb.
Install
pyuvm on PyPI
Before you install
Low friction installation via pip; cocotb is automatically installed as a dependency. The package is actively maintained with recent commits and a stable release history since 2020.
Requires a hardware simulator (e.g., Icarus, VCS, Vivado) and cocotb to be configured; simulation runs through Makefiles that invoke cocotb-config.
License in practice
Licensed under Apache Software License (permissive), allowing commercial and private use with minimal restrictions.
Quickstart
pip install pyuvm
from pyuvm import *
my_object = uvm_object("my_object")
print("object name:", my_object.get_name())
Verify before relying
- Whether all IEEE 1800.2 sections beyond those listed (e.g., Memory, Backdoor access) are planned or out of scope.
- Performance characteristics when running large-scale testbenches compared to SystemVerilog UVM.
- Compatibility matrix with specific simulator versions and cocotb releases.
Package facts
| License | permissive license permissive |
| Python support | Supports the current Python release >=3.6 |
| Install friction | Low. Pure-Python wheel |
| Runtime dependencies | 1 packagecocotb |
| Maintenance | Actively maintained 300 days since the last release |
| Last repo commit | |
| First released | |
| Downloads | 362,935 / month, #7,228 on PyPI 30-day window, as of 2026-08-14 |
| Known vulnerabilities | None known OSV.dev, checked 2026-08-14 |
| Classifiers | Framework :: cocotbLicense :: OSI Approved :: Apache Software LicenseOperating System :: OS IndependentProgramming Language :: Python :: 3Topic :: Scientific/Engineering :: Electronic Design Automation (EDA) |
Evidence: pyuvm-4.0.1-py3-none-any.whl
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See also peakrdl-uvm · cocotb-coverage · cocotb-bus · cocotb-test · pyucis · lambdalib · vonage-network-number-verification · peakrdl-regblock · svql