---
id: pyuvm
version: "4.0.1"
license: unclear
license_treatment: permissive
maintenance: active
---

# pyuvm — A Python implementation of the UVM using cocotb

License: permissive · Maintenance: active · Downloads: 362.9K/mo

## What it is and what it does

pyuvm brings the industry-standard Universal Verification Methodology to Python, implementing the IEEE 1800.2 standard without requiring SystemVerilog. It provides core UVM abstractions—base classes, factory, phasing, transaction-level modeling (TLM), components, sequences, and a register access layer—all designed to work with cocotb to drive hardware simulations. Python's object-oriented features (multiple inheritance, no strict typing, no parameterized classes) make UVM testbench code simpler to write and maintain than the SystemVerilog equivalent.

The package covers the most-used sections of IEEE 1800.2, including base classes, reporting, factory, phasing, TLM interfaces, component hierarchy, sequences, and register blocks. Some advanced features like Memory and atomic Backdoor access remain unimplemented. Testbenches import pyuvm and use cocotb coroutines to interact with simulators, schedule events, and verify RTL designs through reusable, standardized testbench components.

Use it for:

- Build reusable RTL verification testbenches in Python that follow IEEE 1800.2 conventions without learning SystemVerilog.
- Verify hardware designs (Verilog or VHDL) using transaction-level modeling and UVM sequences in a Python environment.
- Develop register verification tests using the register access layer to model and test memory-mapped hardware registers.
- Create portable testbenches that can run across different simulators by leveraging cocotb's simulator abstraction.
- Teach verification methodology to engineers familiar with Python but new to SystemVerilog UVM.

## Worth the install?

AI-flagged interpretation of the facts above — verify before relying.

Implements the IEEE 1800.2 Universal Verification Methodology (UVM) standard in Python, enabling RTL verification testbenches to run through cocotb simulators.

Yes. pyuvm is actively maintained, has no known vulnerabilities, installs with low friction, and is permissively licensed. It is the right choice if you need UVM-compliant verification in Python and have access to a cocotb-compatible simulator. Install it if your team prefers Python over SystemVerilog or if you are building testbenches for projects already using cocotb.

## Install

pip install pyuvm
uv add pyuvm
poetry add pyuvm

## Installing pyuvm

Before you install: Low friction installation via pip; cocotb is automatically installed as a dependency. The package is actively maintained with recent commits and a stable release history since 2020.

License in practice: Licensed under Apache Software License (permissive), allowing commercial and private use with minimal restrictions.

Quickstart:

pip install pyuvm

from pyuvm import *
my_object = uvm_object("my_object")
print("object name:", my_object.get_name())

Requires a hardware simulator (e.g., Icarus, VCS, Vivado) and cocotb to be configured; simulation runs through Makefiles that invoke cocotb-config.

Verify before relying:

- Whether all IEEE 1800.2 sections beyond those listed (e.g., Memory, Backdoor access) are planned or out of scope.
- Performance characteristics when running large-scale testbenches compared to SystemVerilog UVM.
- Compatibility matrix with specific simulator versions and cocotb releases.

## Package facts

- License: not declared (permissive)
- Python support: supports_current
- Install friction: low
- Maintenance: active
- Downloads: 362.9K/month (top 15,000 on PyPI)
- Known vulnerabilities: none known

## Tags

UVM verification in Python, IEEE 1800.2 implementation, cocotb testbench framework, RTL verification methodology, hardware simulation testing, transaction level modeling, register access layer, hardware-verification, uvm-framework, eda

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