lambdalib
Standardized ASIC design libraries
Decision gist · record as of 2026-08-14
Yes, if you are designing ASICs with siliconcompiler and targeting multiple foundry processes or need portable, standardized cell abstractions. The library is actively maintained, MIT-licensed, and proven in production tapeouts. Install it if you want to decouple your RTL from process-specific details; skip it if you are working with a single fixed foundry or using a different ASIC flow entirely.AI-flagged interpretation of the facts on this page — verify before relying
Before you install
- Requires Python >=3.9.
- Designed for use within siliconcompiler workflows; standalone RTL simulation requires external Verilog tools (iverilog, yosys).
- Low friction installation as a pure Python wheel.
License · maintenance · safety
MIT (permissive) — MIT licensed (permissive). Free to use, modify, and integrate into proprietary designs without restriction.
last release 2026-07-08 (37 days) · last repo commit 2026-08-03 · 55 stars
0 known vulnerabilities (OSV.dev, 2026-08-14) · 77,060 downloads/mo, #14,555 on PyPI
Alternatives
Verify before relying
pip install lambdalib
from siliconcompiler import Design
from lambdalib.stdlib import Inv, Dffq
from lambdalib.ramlib import Dpram
class MyChip(Design):
def __init__(self):
super().__init__('mychip')
self.add_depfileset(Inv(), depfileset='rtl', fileset='rtl')
self.add_depfileset(Dffq(), depfileset='rtl', fileset='rtl')- Completeness of cell coverage across all supported foundry technologies (ASAP7, FreePDK45, IHP130, Skywater130, GF180MCU).
- Performance and area characteristics of generated cells relative to foundry-native implementations.
- Compatibility with production signoff flows beyond RTL simulation mentioned in the disclaimer.
What it is and what it does
Lambdalib is a modular cell library for ASIC design that abstracts away technology-specific details—synchronizers, clock gating, I/O pads, memory compilers, and analog blocks—so designers can write portable RTL once and retarget it to different process nodes without redesign. It solves the problem that modern CMOS manufacturing requires different implementations for each foundry, wasting months of engineering time on reimplementation of the same functionality.
The library organizes cells into specialized domains: standard digital logic (97 cells), special-purpose circuits (22 cells), memory modules (6), I/O pads (16), padring generation (3), vectorized datapaths (15), FPGA primitives (3), and analog circuits (2). Each cell is a Python class wrapping Verilog, designed to integrate natively with siliconcompiler's build flow. Designers instantiate cells in RTL using the `la_` prefix, then add them as dependencies to their design; the library handles technology mapping through Lambdapdk for supported processes.
Use it for
- Porting an ASIC design from one foundry process to another without rewriting synchronizers, memory compilers, or I/O pad logic.
- Building a multi-project chip that must support multiple process nodes with a single RTL codebase.
- Rapid prototyping of digital designs using standardized, proven cells instead of writing custom implementations.
- Integrating memory, padring, and clock-domain-crossing logic into a larger design without technology-specific customization.
- Teaching ASIC design methodology with portable, process-independent cell abstractions.
Worth the install?
AI-flagged interpretation of the facts on this page. Verify before relying on it.
Yes, if you are designing ASICs with siliconcompiler and targeting multiple foundry processes or need portable, standardized cell abstractions.
The library is actively maintained, MIT-licensed, and proven in production tapeouts. Install it if you want to decouple your RTL from process-specific details; skip it if you are working with a single fixed foundry or using a different ASIC flow entirely.
Install
lambdalib on PyPI
Before you install
Low friction installation as a pure Python wheel. Actively maintained with recent releases; last commit 2026-08-03. Depends on siliconcompiler and Jinja2, both standard tools in the ASIC design ecosystem.
Requires Python >=3.9. Designed for use within siliconcompiler workflows; standalone RTL simulation requires external Verilog tools (iverilog, yosys).
License in practice
MIT licensed (permissive). Free to use, modify, and integrate into proprietary designs without restriction.
Quickstart
pip install lambdalib
from siliconcompiler import Design
from lambdalib.stdlib import Inv, Dffq
from lambdalib.ramlib import Dpram
class MyChip(Design):
def __init__(self):
super().__init__('mychip')
self.add_depfileset(Inv(), depfileset='rtl', fileset='rtl')
self.add_depfileset(Dffq(), depfileset='rtl', fileset='rtl')Verify before relying
- Completeness of cell coverage across all supported foundry technologies (ASAP7, FreePDK45, IHP130, Skywater130, GF180MCU).
- Performance and area characteristics of generated cells relative to foundry-native implementations.
- Compatibility with production signoff flows beyond RTL simulation mentioned in the disclaimer.
Package facts
| License | MIT permissive |
| Python support | Supports the current Python release >=3.9 |
| Install friction | Low. Pure-Python wheel |
| Runtime dependencies | 2 packagessiliconcompilerJinja2 |
| Maintenance | Actively maintained 37 days since the last release |
| Last repo commit | |
| First released | |
| Downloads | 77,060 / month, #14,555 on PyPI 30-day window, as of 2026-08-14 |
| Known vulnerabilities | None known OSV.dev, checked 2026-08-14 |
Evidence: lambdalib-0.13.1-py3-none-any.whl
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See also lambdapdk · siliconcompiler · peakrdl-regblock · amaranth · systemrdl-compiler · lib · pyuvm · kfactory · salamandra · cocotb