---
id: lambdalib
version: "0.13.1"
license: MIT
license_treatment: permissive
maintenance: active
---

# lambdalib — Standardized ASIC design libraries

License: permissive · Maintenance: active · Downloads: 77.1K/mo

## What it is and what it does

Lambdalib is a modular cell library for ASIC design that abstracts away technology-specific details—synchronizers, clock gating, I/O pads, memory compilers, and analog blocks—so designers can write portable RTL once and retarget it to different process nodes without redesign. It solves the problem that modern CMOS manufacturing requires different implementations for each foundry, wasting months of engineering time on reimplementation of the same functionality.

The library organizes cells into specialized domains: standard digital logic (97 cells), special-purpose circuits (22 cells), memory modules (6), I/O pads (16), padring generation (3), vectorized datapaths (15), FPGA primitives (3), and analog circuits (2). Each cell is a Python class wrapping Verilog, designed to integrate natively with siliconcompiler's build flow. Designers instantiate cells in RTL using the `la_` prefix, then add them as dependencies to their design; the library handles technology mapping through Lambdapdk for supported processes.

Use it for:

- Porting an ASIC design from one foundry process to another without rewriting synchronizers, memory compilers, or I/O pad logic.
- Building a multi-project chip that must support multiple process nodes with a single RTL codebase.
- Rapid prototyping of digital designs using standardized, proven cells instead of writing custom implementations.
- Integrating memory, padring, and clock-domain-crossing logic into a larger design without technology-specific customization.
- Teaching ASIC design methodology with portable, process-independent cell abstractions.

## Worth the install?

AI-flagged interpretation of the facts above — verify before relying.

Lambdalib provides technology-agnostic hardware abstraction for ASIC design, allowing designers to write RTL once and target multiple foundry processes through a library of standardized cells that decouple design from manufacturing specifics.

Yes, if you are designing ASICs with siliconcompiler and targeting multiple foundry processes or need portable, standardized cell abstractions. The library is actively maintained, MIT-licensed, and proven in production tapeouts. Install it if you want to decouple your RTL from process-specific details; skip it if you are working with a single fixed foundry or using a different ASIC flow entirely.

## Install

pip install lambdalib
uv add lambdalib
poetry add lambdalib

## Installing lambdalib

Before you install: Low friction installation as a pure Python wheel. Actively maintained with recent releases; last commit 2026-08-03. Depends on siliconcompiler and Jinja2, both standard tools in the ASIC design ecosystem.

License in practice: MIT licensed (permissive). Free to use, modify, and integrate into proprietary designs without restriction.

Quickstart:

pip install lambdalib

from siliconcompiler import Design
from lambdalib.stdlib import Inv, Dffq
from lambdalib.ramlib import Dpram

class MyChip(Design):
    def __init__(self):
        super().__init__('mychip')
        self.add_depfileset(Inv(), depfileset='rtl', fileset='rtl')
        self.add_depfileset(Dffq(), depfileset='rtl', fileset='rtl')

Requires Python >=3.9. Designed for use within siliconcompiler workflows; standalone RTL simulation requires external Verilog tools (iverilog, yosys).

Verify before relying:

- Completeness of cell coverage across all supported foundry technologies (ASAP7, FreePDK45, IHP130, Skywater130, GF180MCU).
- Performance and area characteristics of generated cells relative to foundry-native implementations.
- Compatibility with production signoff flows beyond RTL simulation mentioned in the disclaimer.

## Package facts

- License: MIT (permissive)
- Python support: supports_current
- Install friction: low
- Maintenance: active
- Downloads: 77.1K/month (top 15,000 on PyPI)
- Known vulnerabilities: none known

## Tags

hardware abstraction library asic, technology-agnostic cell library, portable asic design, foundry-independent rtl cells, process node porting, standardized asic cells, lambdalib siliconcompiler, asic-design, hardware-abstraction, cell-library

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