siliconcompiler

What it is and what it does

SiliconCompiler is a Python-based hardware build system that orchestrates the entire design flow from RTL (Verilog, SystemVerilog, VHDL, Chisel, MLIR) to fabrication-ready GDS. It abstracts over many industry EDA tools—synthesis (Yosys, Vivado, Synopsys), place-and-route (OpenROAD, VPR, nextpnr), simulation (Verilator, Icarus, GHDL), and DRC/LVS—through a unified Python API and dynamic JSON schema. The system supports ASIC design, FPGA builds, simulation, and linting, with built-in support for open PDKs (sky130, ihp130, gf180, asap7) via lambdapdk.

The package is designed to "make the complex possible while keeping the simple simple": a basic ASIC flow takes 13 lines of Python, yet the tool scales to commercial tapeouts at advanced nodes. It includes a remote execution model to avoid local tool installation, automatic compilation manifests for provenance, and a modular tool abstraction layer for adding new EDA tools. With 22 runtime dependencies (aiohttp, docker, pandas, Jinja2, PyYAML, etc.), it handles networking, containerization, templating, and data processing internally.

Use it for:

• Lint RTL designs without installing any EDA tools—the default linter ships as pure Python.
• Automate ASIC design flows from RTL to DRC-clean GDS using open PDKs (sky130, gf180) or foundry PDKs.
• Build FPGA bitstreams with Yosys, VPR, or nextpnr through a single Python interface.
• Run formal verification and simulation (Verilator, GHDL, SymbiYosys) as part of a unified design flow.
• Execute hardware builds remotely or in Docker to avoid local tool installation and enable cloud-scale compilation.
• Integrate hardware design into CI/CD pipelines using the programmatic Python API and automatic manifests.

Worth the install?

AI-flagged interpretation of the facts on this page — verify before relying

SiliconCompiler is a modular hardware build system that automates translation from source code (RTL, Chisel, MLIR, etc.) to silicon through a programmable Python API, supporting ASIC, FPGA, simulation, and linting workflows.

Yes. SiliconCompiler is actively maintained, has no known vulnerabilities, and offers low install friction (pure Python wheel). It is a mature, production-grade tool used for commercial tapeouts. Install it if you need to automate hardware design flows, integrate RTL-to-GDS into CI/CD, or explore ASIC/FPGA design without managing many EDA tools separately. The Apache-2.0 license poses no restrictions.

Install

siliconcompiler on PyPI

pip install siliconcompiler

uv add siliconcompiler

poetry add siliconcompiler

Installing siliconcompiler

Before you install

Low friction: pure Python wheel with no compiled dependencies. Active maintenance (last commit 2026-08-14, 1199 GitHub stars). Requires Python 3.10–3.14. Most EDA tools are optional; linting works out-of-the-box. Remote execution available to avoid local tool installation.

License in practice

Apache-2.0 (permissive): you can use, modify, and distribute SiliconCompiler freely in commercial and open-source projects, with minimal restrictions beyond attribution and liability disclaimers.

Quickstart

pip install siliconcompiler

from siliconcompiler import ASIC, Design
from siliconcompiler.targets import skywater130_demo

design = Design("heartbeat")
design.set_topmodule("heartbeat", fileset="rtl")
design.add_file("heartbeat.v", fileset="rtl")
project = ASIC(design)
skywater130_demo(project)
project.run()

Requires Python 3.10 or later. Full ASIC/FPGA flows require external EDA tools (Yosys, OpenROAD, etc.); linting and remote execution work without local tools installed.

Verify before relying

• Whether remote execution is available by default or requires additional setup/credentials.
• Specific performance characteristics or scalability limits for large designs.
• Whether foundry PDK packaging (gf12lp, gf22fdx, intel16) requires proprietary agreements beyond what the package provides.

Package facts

Evidence: siliconcompiler-0.38.4-py3-none-any.whl

Tags

More Build Tools packages