edalize
Library for interfacing EDA tools such as simulators, linters or synthesis tools, using a common interface
What it is and what it does
Edalize is a Python library that provides a unified interface to Electronic Design Automation (EDA) tools—simulators like Icarus and ModelSim, synthesis tools like Vivado and Quartus, and linters. Instead of learning each tool's specific project format and command-line interface, you describe your HDL design once (files, parameters, constraints) and Edalize generates the necessary tool-specific project files and orchestrates building and running them.
The library accepts Verilog and VHDL source files, tool-specific options, compile-time parameters (Verilog defines, generics), and runtime arguments (plusargs), then creates and executes projects in your chosen tool. This is particularly useful for switching between simulators to verify tool-specific behavior or for automating repetitive HDL workflows. It can be embedded in Python projects or used to generate template files for manual GUI work.
Use it for:
- Run the same HDL testbench across multiple simulators (Icarus, ModelSim, Xsim) to verify tool-independent correctness
- Automate FPGA synthesis and place-and-route for Xilinx or Altera tools from a single project definition
- Generate simulator project files for manual inspection or GUI-based debugging without writing tool-specific scripts
- Parameterize HDL simulations with compile-time and runtime arguments, then sweep parameters across multiple runs
- Integrate HDL verification into Python-based CI/CD pipelines without tool-specific build logic
Worth the install?
AI-flagged interpretation of the facts on this page — verify before relying
Edalize abstracts the interface to EDA tools (simulators, synthesis tools, linters) so you can define a project once and run it across different tools without rewriting tool-specific configurations.
Yes. Edalize is actively maintained, has no known vulnerabilities, installs with minimal friction, and solves a real problem for HDL workflows—abstracting away tool-specific boilerplate. If you work with multiple EDA tools or need to automate HDL builds, it will save significant effort. If you use only one tool and have no automation needs, the value is lower.
Install
edalize on PyPI
pip
pip install edalizeuv
uv add edalizepoetry
poetry add edalizeInstalling edalize
Before you install
Low friction install with only two runtime dependencies (Jinja2 and importlib_metadata). Actively maintained with recent releases; last commit 2026-08-12 and repository not archived.
License in practice
Permissive license treatment means you can use, modify, and distribute this package with minimal legal restrictions, making it suitable for both open and proprietary projects.
Quickstart
pip install edalize
from edalize import get_edatool
import os
files = [{'name': 'design.v', 'file_type': 'verilogSource'}]
edam = {'files': files, 'name': 'project', 'toplevel': 'top'}
backend = get_edatool('icarus')(edam=edam, work_root='build')
os.makedirs('build')
backend.configure()
backend.build()
Requires Python 3.9 or later. The actual EDA tools (Icarus, Vivado, ModelSim, etc.) must be installed separately and available in your PATH.
Verify before relying
- Which specific EDA tools are supported in version 0.6.8 and their minimum versions
- Whether optional reporting modules require additional dependencies beyond the core install
- Performance characteristics when handling large HDL projects or many tool invocations
Package facts
| License | not declared (permissive) |
| Python support | supports the current Python release (<4,>=3.9) |
| Install friction | low — pure-Python wheel |
| Runtime dependencies | 2 — Jinja2, importlib_metadata |
| Maintenance | actively maintained — 112 days since the last release |
| Last repo commit | |
| First released | |
| Downloads | 220,261/month — #9,307 on PyPI (30-day window, as of 2026-08-14) |
| Known vulnerabilities | none known (OSV.dev, checked 2026-08-14) |
Evidence: edalize-0.6.8-py3-none-any.whl
Keywords: VHDL, verilog, EDA, hdl, rtl, synthesis, FPGA, simulation, Xilinx, Altera
Tags
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