{"categories":[{"label":"Electronic Design Automation (EDA)","url":"https://skillfed.io/packages/category/scientific-engineering-electronic-design-automation-eda"}],"enrichment":{"capability":"Implements the IEEE 1800.2 Universal Verification Methodology (UVM) standard in Python, enabling RTL verification testbenches to run through cocotb simulators.","skillfed_tags":["hardware-verification","uvm-framework","eda"],"use_cases":["Build reusable RTL verification testbenches in Python that follow IEEE 1800.2 conventions without learning SystemVerilog.","Verify hardware designs (Verilog or VHDL) using transaction-level modeling and UVM sequences in a Python environment.","Develop register verification tests using the register access layer to model and test memory-mapped hardware registers.","Create portable testbenches that can run across different simulators by leveraging cocotb's simulator abstraction.","Teach verification methodology to engineers familiar with Python but new to SystemVerilog UVM."],"what_it_does":"pyuvm brings the industry-standard Universal Verification Methodology to Python, implementing the IEEE 1800.2 standard without requiring SystemVerilog. It provides core UVM abstractions\u2014base classes, factory, phasing, transaction-level modeling (TLM), components, sequences, and a register access layer\u2014all designed to work with cocotb to drive hardware simulations. Python's object-oriented features (multiple inheritance, no strict typing, no parameterized classes) make UVM testbench code simpler to write and maintain than the SystemVerilog equivalent.\n\nThe package covers the most-used sections of IEEE 1800.2, including base classes, reporting, factory, phasing, TLM interfaces, component hierarchy, sequences, and register blocks. Some advanced features like Memory and atomic Backdoor access remain unimplemented. Testbenches import pyuvm and use cocotb coroutines to interact with simulators, schedule events, and verify RTL designs through reusable, standardized testbench components.","worth_installing":"Yes. pyuvm is actively maintained, has no known vulnerabilities, installs with low friction, and is permissively licensed. It is the right choice if you need UVM-compliant verification in Python and have access to a cocotb-compatible simulator. Install it if your team prefers Python over SystemVerilog or if you are building testbenches for projects already using cocotb."},"id":"pyuvm","links":{"html":"https://skillfed.io/packages/pyuvm","md":"https://skillfed.io/packages/pyuvm.md","pypi":"https://pypi.org/project/pyuvm/"},"maintenance":{"status":"active"},"meta":{"latest_release":"2025-10-18","license_spdx":null,"license_treatment":"permissive","name":"pyuvm","python_support":"supports_current","summary":"A Python implementation of the UVM using cocotb"},"popularity":{"monthly_downloads":362935,"position":7228,"tier":"top_15000"},"security":{"n_vulnerabilities":0},"version":"4.0.1"}