peakrdl-cheader
Generate C Header files from a SystemRDL register model
Decision gist · record as of 2026-08-14
Yes. The package is production-stable, actively maintained, has low install friction, and solves a real problem in hardware-software co-development. The LGPLv3 copyleft license is standard for open-source tools and poses no barrier for most use cases. Install it if you work with SystemRDL register models and need C headers.AI-flagged interpretation of the facts on this page — verify before relying
Before you install
- Requires a valid SystemRDL input file and systemrdl-compiler to parse it; jinja2 is used internally for template rendering.
- Low install friction with a pure Python wheel.
- Actively maintained as of March 2026 with recent commits.
License · maintenance · safety
LGPLv3 (copyleft) — Licensed under LGPLv3 (copyleft). You may use and modify the package freely, but any derivative work must also be licensed under LGPLv3 and source code must be made available.
last release 2026-03-28 (139 days) · last repo commit 2026-03-28 · 16 stars
0 known vulnerabilities (OSV.dev, 2026-08-14) · 231,501 downloads/mo, #9,085 on PyPI
Alternatives
Verify before relying
pip install peakrdl-cheader
from peakrdl.cheader import CHeaderCompiler
from systemrdl import RDLCompiler
rdl = RDLCompiler()
rdl.compile_file('registers.rdl')
compiler = CHeaderCompiler(rdl.root)
compiler.write('output.h')- Whether the package supports incremental compilation or batch processing of multiple register models
- What C standard or dialect the generated headers target
- Whether generated headers include register access macros or only struct definitions
What it is and what it does
PeakRDL C Header is a code generator that converts SystemRDL register specifications into C header files. It sits on top of the systemrdl-compiler to parse hardware register definitions and uses jinja2 templates to produce C code. The package is designed for hardware-software co-development workflows where register layouts defined in SystemRDL need to be exposed to C firmware or driver code.
The tool is part of the broader PeakRDL ecosystem and targets developers working with register-level hardware abstractions. It automates the error-prone manual translation of register specifications into C headers, ensuring consistency between hardware documentation and software code. The package is production-stable, actively maintained, and has no known security vulnerabilities.
Use it for
- Generate C headers from SystemRDL register models for embedded firmware development
- Automate register definition synchronization between hardware specs and C driver code
- Create consistent register access structures for SoC bring-up and validation
- Integrate register code generation into hardware-software build pipelines
Worth the install?
AI-flagged interpretation of the facts on this page. Verify before relying on it.
Yes.
The package is production-stable, actively maintained, has low install friction, and solves a real problem in hardware-software co-development. The LGPLv3 copyleft license is standard for open-source tools and poses no barrier for most use cases. Install it if you work with SystemRDL register models and need C headers.
Install
peakrdl-cheader on PyPI
Before you install
Low install friction with a pure Python wheel. Actively maintained as of March 2026 with recent commits. Depends on systemrdl-compiler and jinja2, both stable and widely available.
Requires a valid SystemRDL input file and systemrdl-compiler to parse it; jinja2 is used internally for template rendering.
License in practice
Licensed under LGPLv3 (copyleft). You may use and modify the package freely, but any derivative work must also be licensed under LGPLv3 and source code must be made available.
Quickstart
pip install peakrdl-cheader
from peakrdl.cheader import CHeaderCompiler
from systemrdl import RDLCompiler
rdl = RDLCompiler()
rdl.compile_file('registers.rdl')
compiler = CHeaderCompiler(rdl.root)
compiler.write('output.h')
Verify before relying
- Whether the package supports incremental compilation or batch processing of multiple register models
- What C standard or dialect the generated headers target
- Whether generated headers include register access macros or only struct definitions
Package facts
| License | LGPLv3 copyleft |
| Python support | Supports the current Python release >=3.7 |
| Install friction | Low. Pure-Python wheel |
| Runtime dependencies | 2 packagessystemrdl-compilerjinja2 |
| Maintenance | Actively maintained 139 days since the last release |
| Last repo commit | |
| First released | |
| Downloads | 231,501 / month, #9,085 on PyPI 30-day window, as of 2026-08-14 |
| Known vulnerabilities | None known OSV.dev, checked 2026-08-14 |
| Classifiers | Development Status :: 5 - Production/StableIntended Audience :: DevelopersLicense :: OSI Approved :: GNU Lesser General Public License v3 (LGPLv3)Operating System :: OS IndependentProgramming Language :: PythonProgramming Language :: Python :: 3Programming Language :: Python :: 3 :: OnlyTopic :: Scientific/Engineering :: Electronic Design Automation (EDA) |
Evidence: peakrdl_cheader-1.1.0-py3-none-any.whl
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See also peakrdl-python · peakrdl-systemrdl · peakrdl-html · peakrdl-regblock · peakrdl-cli · peakrdl · peakrdl-uvm · pyvcd