{"categories":[{"label":"Electronic Design Automation (EDA)","url":"https://skillfed.io/packages/category/scientific-engineering-electronic-design-automation-eda"}],"enrichment":{"capability":"PeakRDL is a control and status register (CSR) generator toolchain that processes SystemRDL register descriptions and generates synthesizable SystemVerilog RTL, C register headers, HTML documentation, UVM models, and IP-XACT exports.","skillfed_tags":["hardware-design","code-generation","eda"],"use_cases":["Generate synthesizable Verilog register blocks from a single SystemRDL source, reducing manual RTL coding and synchronization errors.","Produce C register abstraction headers automatically, keeping firmware and hardware register definitions in sync.","Create rich HTML register documentation directly from register descriptions for design reviews and handoff.","Import and export IP-XACT XML to integrate with other EDA tools and design flows.","Build UVM register models for simulation-based verification without manual abstraction layer coding.","Extend the toolchain with custom plugins to generate project-specific register artifacts or integrate with proprietary tools."],"what_it_does":"PeakRDL is a free, open-source toolchain for automating control and status register (CSR) generation in hardware and firmware projects. It reads SystemRDL 2.0 register descriptions\u2014a domain-specific language for defining register layouts\u2014and generates multiple artifacts: synthesizable SystemVerilog RTL register blocks, C register abstraction headers for software, HTML documentation, UVM register models for verification, and IP-XACT XML for interoperability. The tool is extensible via plugins, allowing teams to add custom code generators or integrate with their existing design flows.\n\nThe package is production-stable, actively maintained, and widely used in FPGA and ASIC design flows. It supports current Python versions (3.7+) and has no known security vulnerabilities. The core framework is lightweight and pure Python, making installation straightforward. Most users will pair it with one or more of the provided plugins (for Verilog generation, C headers, HTML docs, etc.) depending on their workflow needs.","worth_installing":"Yes. PeakRDL is a mature, actively maintained tool with low install friction and no security issues. It solves a real problem in hardware design\u2014automating register generation and keeping hardware and software definitions synchronized. The copyleft license (LGPLv3) is standard for open-source EDA tools and poses no barrier for open-source or internal projects; commercial users should review license terms. Install it if your workflow involves SystemRDL or register automation."},"id":"peakrdl","links":{"html":"https://skillfed.io/packages/peakrdl","md":"https://skillfed.io/packages/peakrdl.md","pypi":"https://pypi.org/project/peakrdl/"},"maintenance":{"status":"active"},"meta":{"latest_release":"2025-10-03","license_spdx":null,"license_treatment":"copyleft","name":"peakrdl","python_support":"supports_current","summary":"Toolchain for control/status register automation and code generation."},"popularity":{"monthly_downloads":207376,"position":9554,"tier":"top_15000"},"security":{"n_vulnerabilities":0},"version":"1.5.0"}