{"categories":[{"label":"Utilities","url":"https://skillfed.io/packages/category/utilities/7"},{"label":"Build Tools","url":"https://skillfed.io/packages/category/software-development-build-tools/3"}],"enrichment":{"capability":"FuseSoC is a package manager and build abstraction tool for HDL code that enables reuse of IP cores, manages hardware designs, and coordinates builds and simulations across multiple tools and targets.","skillfed_tags":["hdl-tools","fpga-workflow","ip-management"],"use_cases":["Manage a library of reusable Verilog or VHDL IP cores and automatically resolve dependencies when building a larger design.","Run regression tests on hardware designs against multiple simulators without manually switching tool configurations.","Port an existing FPGA design to a new development board by updating target definitions rather than rewriting build scripts.","Set up continuous integration for hardware projects to automatically build and simulate designs on every commit.","Generate FPGA software bills of materials (SBOMs) through the spdxgen filter for compliance and documentation.","Perform linting and formal verification on hardware code as part of an automated design flow."],"what_it_does":"FuseSoC is a build and package management system designed for hardware description languages like Verilog and VHDL. It abstracts away the differences between various HDL tools and simulators, allowing you to define hardware designs once and build or simulate them across multiple toolchains and FPGA targets without rewriting build scripts. The core problem it solves is IP reuse and design portability\u2014instead of managing separate build configurations for each simulator or target, you describe your design in FuseSoC's core file format and let it handle tool invocation, dependency resolution, and parameter configuration.\n\nFuseSoC is typically used in three contexts: managing libraries of reusable hardware IP cores, orchestrating builds and simulations in continuous integration pipelines, and porting existing designs to new FPGA boards or tool versions. It integrates with tools like Vivado, Quartus, and open-source simulators, and supports formal verification, linting, and SBOM generation. The package is production-stable, actively maintained, and widely used in both open-source hardware projects and commercial ASIC/FPGA development.","worth_installing":"Yes. FuseSoC is a mature, actively maintained tool with no known vulnerabilities, low install friction, and permissive licensing. It is well-suited for anyone managing HDL projects, especially those needing to coordinate builds across multiple tools, reuse IP cores, or set up reproducible hardware build pipelines. Install it if you work with Verilog, VHDL, or SoC design; skip it if you only use a single closed-source tool with its own build system."},"id":"fusesoc","links":{"html":"https://skillfed.io/packages/fusesoc","md":"https://skillfed.io/packages/fusesoc.md","pypi":"https://pypi.org/project/fusesoc/"},"maintenance":{"status":"active"},"meta":{"latest_release":"2026-05-10","license_spdx":null,"license_treatment":"permissive","name":"fusesoc","python_support":"supports_current","summary":"Award-winnning package manager and build abstraction tool for HDL code"},"popularity":{"monthly_downloads":242183,"position":8861,"tier":"top_15000"},"security":{"n_vulnerabilities":0},"version":"2.4.6"}