---
id: svql
version: "0.1.9"
license: MIT
license_treatment: permissive
maintenance: aging
---

# svql — Query SystemVerilog modules with SQL.

License: permissive · Maintenance: aging · Downloads: 76.9K/mo

## What it is and what it does

svql is a Python tool that parses SystemVerilog module files and makes their structural information—parameters, ports, and connections—queryable via SQL. It wraps the pyslang parser to extract module metadata and stores it in pandas DataFrames, then uses pandasql to let you write SQL SELECT queries against those tables. The typical workflow is to load a .sv file, call module.query() with a SQL statement, and get back a DataFrame of results.

This is useful for hardware engineers and design automation workflows where you need to inspect or extract specific details from RTL modules without manually reading the source. The aging maintenance status and lack of recent activity suggest the project is stable but not actively developed; it works well for its narrow purpose but may not receive updates for new SystemVerilog standards or edge cases.

Use it for:

- Extract all parameters with default values from a module to understand its configuration points.
- Query input or output ports by direction to document or validate a module's interface.
- Identify which parameters have been overridden in a specific instantiation versus left at defaults.
- Automate RTL documentation by querying port widths, types, and connectivity across modules.
- Build design verification scripts that programmatically inspect module structure without parsing SystemVerilog by hand.

## Worth the install?

AI-flagged interpretation of the facts above — verify before relying.

Parses SystemVerilog modules and exposes their parameters, ports, and connections as SQL-queryable DataFrames for analysis and extraction.

Yes, if you work with SystemVerilog and need to query module structure programmatically. Install friction is low and the license is permissive. However, the aging maintenance status means you should verify that pyslang handles your specific SystemVerilog dialect and features before committing to it in a critical workflow; no vulnerabilities are known, but don't expect rapid fixes if issues arise.

## Install

pip install svql
uv add svql
poetry add svql

## Installing svql

Before you install: Low friction: pure Python wheel with only three runtime dependencies (pandas, pandasql, pyslang). Maintenance status is aging—last release was in early March 2025 with no recent commits visible—so expect limited active support for bug fixes or new features.

License in practice: MIT license is permissive, allowing commercial and private use with minimal restrictions; you may use, modify, and distribute this package freely as long as you include the original license notice.

Quickstart:

from svql import Module

module = Module("path/to/module.sv")
result = module.query("SELECT * FROM params WHERE override_value IS NULL")
print(result)

Requires a valid SystemVerilog file path; pyslang (a SystemVerilog parser) must be able to parse the target file without syntax errors.

Verify before relying:

- Whether pyslang's parsing covers all SystemVerilog constructs or has known limitations that would affect real-world modules.
- Performance characteristics when querying large or complex modules with many parameters and ports.
- Whether the package handles SystemVerilog 2017/2023 features or is limited to earlier standards.

## Package facts

- License: MIT (permissive)
- Python support: supports_current
- Install friction: low
- Maintenance: aging
- Downloads: 76.9K/month (top 15,000 on PyPI)
- Known vulnerabilities: none known

## Tags

systemverilog parsing sql, verilog module analysis, hardware design query tool, systemverilog parameter extraction, verilog port inspection, rtl module querying, systemverilog dataframe analysis, hardware-design, rtl-analysis, sql-query

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