---
id: pyslang
version: "11.0.0"
license: Copyright (c) 2015-2026 Michael Popoloski Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in… (full text in the JSON record)
license_treatment: permissive
maintenance: active
---

# pyslang — Python bindings for slang, a library for compiling SystemVerilog

License: permissive · Maintenance: active · Downloads: 455.5K/mo

## What it is and what it does

pyslang is a Python interface to the slang SystemVerilog compiler, a high-performance front end for hardware design language processing. It allows you to load and inspect the syntax tree of SystemVerilog files, evaluate expressions in a scripting context, and access detailed information about modules, ports, declarations, and types. The underlying slang library handles lexing, parsing, type checking, and elaboration of SystemVerilog code with emphasis on compliance and robustness.

You use pyslang when you need to programmatically analyze or transform SystemVerilog designs—for example, extracting module hierarchies, validating code structure, generating reports, or building custom linting and refactoring tools. It has no runtime dependencies and is distributed as precompiled wheels for common platforms, making installation straightforward on supported Python versions.

Use it for:

- Extract and inspect module hierarchies, port lists, and signal declarations from existing SystemVerilog designs.
- Build custom linting or code-quality tools that need to understand SystemVerilog syntax and semantics.
- Generate SystemVerilog code or documentation by traversing and analyzing the parsed syntax tree.
- Evaluate SystemVerilog expressions and constraints in a scripting context without a full simulator.
- Integrate SystemVerilog parsing into editor plugins or language servers for real-time syntax checking.

## Worth the install?

AI-flagged interpretation of the facts above — verify before relying.

pyslang provides Python bindings to parse, analyze, and elaborate SystemVerilog code, exposing the underlying slang compiler's syntax tree and evaluation capabilities for programmatic inspection and manipulation.

Yes, if you work with SystemVerilog and need programmatic access to parsing and analysis. The package is actively maintained, has no known vulnerabilities, carries a permissive MIT license, and offers precompiled wheels for modern Python on major platforms. Medium install friction is acceptable given the complexity of compiling a C++ SystemVerilog parser. Not necessary if you only need command-line compilation or linting.

## Install

pip install pyslang
uv add pyslang
poetry add pyslang

## Installing pyslang

Before you install: Medium friction: precompiled wheels available for multiple Python versions on macOS (arm64, universal2), Linux (aarch64, x86_64), and Windows (amd64). Maintenance is active with recent releases and steady repository activity.

License in practice: MIT license permits commercial and private use, modification, and distribution with minimal restrictions—only requiring preservation of copyright and license notices. No notable constraints for most use cases.

Quickstart:

pip install pyslang

import pyslang

tree = pyslang.SyntaxTree.fromFile('design.sv')
mod = tree.root.members[0]
print(mod.header.name.value)

Requires a SystemVerilog source file to parse.

Verify before relying:

- Exact minimum Python version not specified in metadata; wheels available but earliest version unclear.
- Performance characteristics and memory usage on large projects not quantified in the fact sheet.
- Completeness of SystemVerilog feature coverage beyond the reference to sv-lang.com/language-support.html.

## Package facts

- License: Copyright (c) 2015-2026 Michael Popoloski Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in… (full text in the JSON record) (permissive)
- Python support: unspecified
- Install friction: medium
- Maintenance: active
- Downloads: 455.5K/month (top 15,000 on PyPI)
- Known vulnerabilities: none known

## Tags

systemverilog parser python, verilog syntax tree analysis, hdl language bindings, systemverilog compiler frontend, eda python library, verilog ast inspection, systemverilog elaboration, hdl-design, compiler-frontend, eda

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