---
id: peakrdl-uvm
version: "2.4.0"
license: LGPLv3
license_treatment: copyleft
maintenance: aging
---

# peakrdl-uvm — Generate UVM register model from compiled SystemRDL input

License: copyleft · Maintenance: aging · Downloads: 160.0K/mo

## What it is and what it does

PeakRDL-uvm is a code generator that converts compiled SystemRDL register specifications into ready-to-use UVM register models in SystemVerilog. It sits downstream of the systemrdl-compiler, taking an elaborated register tree and emitting either a SystemVerilog package or header file containing UVM register classes, fields, and memories that mirror the original register layout. The tool supports optional features like UVM factory integration, class definition reuse, and user-defined template overrides via jinja2.

It is primarily used as a plugin to the PeakRDL command-line tool, though it can also be invoked directly from Python code. The generated UVM models are meant to accelerate hardware verification by automating the creation of the register abstraction layer—a tedious and error-prone task when done by hand—allowing verification engineers to focus on testbench logic rather than register boilerplate.

Use it for:

- Generate UVM register models from SystemRDL specifications in a CI/CD pipeline to keep testbenches synchronized with register changes.
- Automate register abstraction layer creation for complex SoCs with hundreds of registers across multiple address maps.
- Customize generated UVM classes via user-defined templates to match project-specific verification patterns or naming conventions.
- Export register models as includable headers for integration into existing UVM testbenches without package namespace constraints.
- Enable reuse of register class definitions across multiple design instances to reduce generated code size and compilation time.

## Worth the install?

AI-flagged interpretation of the facts above — verify before relying.

Generates UVM (Universal Verification Methodology) register models in SystemVerilog from compiled SystemRDL register descriptions, enabling automated hardware verification testbench creation.

Yes, if you work with SystemRDL-based hardware designs and need UVM testbenches. The package is stable (Production/Stable classifier), has no known vulnerabilities, and low install friction. The copyleft license is a consideration for proprietary flows—verify compliance before use. Aging maintenance (262 days since last release) is typical for mature tools but means slower response to new UVM or SystemVerilog standards.

## Install

pip install peakrdl-uvm
uv add peakrdl-uvm
poetry add peakrdl-uvm

## Installing peakrdl-uvm

Before you install: Low friction installation with only two runtime dependencies (systemrdl-compiler and jinja2). Maintenance status is aging—last release was 262 days ago—but the repository remains active and unarchived with a modest user base of 61 stars.

License in practice: Licensed under LGPLv3 (copyleft). You must distribute source code and license terms if you distribute derivative works or modifications; using it as a library in proprietary tools requires careful compliance review.

Quickstart:

from systemrdl import RDLCompiler
from peakrdl_uvm import UVMExporter

rdlc = RDLCompiler()
rdlc.compile_file("design.rdl")
root = rdlc.elaborate()

exporter = UVMExporter()
exporter.export(root, "output.sv")

Requires systemrdl-compiler to parse and elaborate SystemRDL files before export; Python >=3.7.

Verify before relying:

- Whether custom template overrides and context variables are documented with examples beyond the API reference.
- Support status for UVM versions and SystemVerilog standard compliance levels.
- Performance characteristics with large register hierarchies or complex designs.

## Package facts

- License: LGPLv3 (copyleft)
- Python support: supports_current
- Install friction: low
- Maintenance: aging
- Downloads: 160.0K/month (top 15,000 on PyPI)
- Known vulnerabilities: none known

## Tags

uvm register model generation, systemrdl to systemverilog, hardware register verification, uvm testbench automation, register abstraction layer generator, systemrdl compiler plugin, csr verification uvm, hardware-verification, register-generation, systemverilog

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