---
id: dvsim
version: "1.50.1"
license: Apache-2.0
license_treatment: permissive
maintenance: active
---

# dvsim — DV system

License: permissive · Maintenance: active · Downloads: 82.0K/mo

## What it is and what it does

DVSim is a standardized command-line interface and orchestration layer for running EDA (Electronic Design Automation) tool flows in ASIC and chip design projects. It wraps multiple verification and synthesis steps—simulations, formal property verification, lint checking, synthesis, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) analysis—into a single, repeatable workflow. Originally developed for the OpenTitan open-source Root of Trust project, it generalizes to any ASIC project.

The package depends on common Python tools for visualization (matplotlib, plotly), configuration (pyyaml, hjson, toml, pydantic), templating (jinja2), and CLI interaction (click, enlighten). It generates reports and badges (anybadge) and integrates with git workflows. Installation is straightforward via pip into a virtual environment, though practical use requires access to EDA tools and design files in a hardware development environment.

Use it for:

- Automate and standardize simulation runs across multiple testbenches in a chip design project
- Run formal verification and connectivity checks as part of a continuous integration pipeline
- Execute lint and synthesis flows with consistent tool configurations and reporting
- Generate coverage reports and unreachability analysis for design verification sign-off
- Orchestrate multi-step EDA workflows (e.g., lint → synthesis → formal) from a single command

## Worth the install?

AI-flagged interpretation of the facts above — verify before relying.

DVSim is a Python-based build and run system that orchestrates EDA tool flows for ASIC design verification, including simulations, formal verification, lint, synthesis, and coverage analysis.

Yes, if you are working on ASIC or chip design verification. DVSim is actively maintained, has no known vulnerabilities, and low install friction. It solves a real problem in hardware design by standardizing EDA tool orchestration. Install it if your project uses multiple EDA flows; it is not useful for general software development or outside hardware design contexts.

## Install

pip install dvsim
uv add dvsim
poetry add dvsim

## Installing dvsim

Before you install: Low install friction with a pure-wheel distribution. Actively maintained with a release 7 days ago. Requires Python 3.10 or later and brings in 14 runtime dependencies including plotting, YAML parsing, and CLI tools.

License in practice: Apache License 2.0 (permissive) allows commercial and private use with minimal restrictions; you must retain license notices and provide a copy of the license.

Quickstart:

pip install dvsim

from dvsim import DVSim
# Then use dvsim command-line tool to run EDA flows

Requires Python 3.10 or later. Designed for ASIC projects with EDA tools; primarily useful in hardware design environments.

Verify before relying:

- Whether DVSim can be used standalone or requires external EDA tools (Synopsys, Cadence, etc.) to be pre-installed
- Specific EDA tool versions or platforms supported beyond the flow types listed
- Whether the package includes example projects or requires user-provided design files

## Package facts

- License: Apache-2.0 (permissive)
- Python support: supports_current
- Install friction: low
- Maintenance: active
- Downloads: 82.0K/month (top 15,000 on PyPI)
- Known vulnerabilities: none known

## Tags

EDA tool flow automation, ASIC design verification, simulation and formal verification runner, design verification build system, chip design workflow orchestration, hardware verification framework, lint synthesis coverage automation, hardware-design, eda-tools, asic-verification

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