---
id: amaranth
version: "0.5.9"
license: BSD-2-clause
license_treatment: permissive
maintenance: active
---

# amaranth — Amaranth hardware definition language

License: permissive · Maintenance: active · Downloads: 81.8K/mo

## What it is and what it does

Amaranth is a Python-based hardware definition language that lets you write FPGA and ASIC designs in Python instead of Verilog or VHDL. It includes a simulator, build system, and standard library, covering the full FPGA development workflow. The language aims to reduce common hardware design mistakes and support reusable component design. Amaranth can target any FPGA or ASIC process accepting behavioral Verilog-2001, with extended support for Lattice (iCE40, MachXO, ECP5, Nexus), AMD (Virtex, Spartan, 7-series, UltraScale), Altera, and Quicklogic families. Existing Verilog or VHDL code can be integrated into an Amaranth design flow, and vice versa. The toolchain is actively maintained and supported by LambdaConcept, ChipEleven, and Chipflow.

Use it for:

- Design FPGA logic for embedded systems or research projects using Python instead of learning Verilog
- Build reusable hardware components and libraries that can be composed into larger designs
- Simulate digital logic behavior before synthesis to catch design errors early
- Integrate Python-generated Verilog into existing Verilog-based design flows
- Target multiple FPGA families from a single Python codebase with vendor-specific toolchain integration

## Worth the install?

AI-flagged interpretation of the facts above — verify before relying.

Amaranth is a Python-based hardware definition language and toolchain for designing synchronous digital logic that targets FPGAs and ASICs, with integrated simulation, build system, and support for multiple vendor platforms.

Yes. Amaranth is actively maintained, has low install friction, permissive licensing, and fills a genuine niche for developers who prefer Python for hardware design. It's suitable for anyone targeting FPGAs or ASICs who wants to avoid Verilog/VHDL syntax and leverage Python's expressiveness. No known security vulnerabilities. The main prerequisite is familiarity with digital logic and access to external synthesis toolchains.

## Install

pip install amaranth
uv add amaranth
poetry add amaranth

## Installing amaranth

Before you install: Low friction: pure Python wheel with four runtime dependencies (importlib_resources, jschon, pyvcd, Jinja2). Actively maintained—last commit 2026-08-12, release 29 days old, 2067 repository stars.

License in practice: BSD-2-clause permissive license allows use in both open-source and proprietary designs, provided the copyright notice is retained.

Quickstart:

pip install amaranth

from amaranth import *
from amaranth.back import verilog

m = Module()
m.d.comb += []
print(verilog.convert(m, ports=[]))

Requires Python ~=3.8. Verilog generation and synthesis require external toolchains (Yosys, nextpnr, vendor tools) depending on target FPGA family.

Verify before relying:

- Whether the simulator supports co-simulation with external tools or testbenches
- Performance characteristics for large designs (gate count, synthesis time)
- Availability of pre-built board definitions and SoC toolkit components

## Package facts

- License: BSD-2-clause (permissive)
- Python support: supports_current
- Install friction: low
- Maintenance: active
- Downloads: 81.8K/month (top 15,000 on PyPI)
- Known vulnerabilities: none known

## Tags

python hardware definition language, fpga design python, hdl toolchain, digital logic synthesis, verilog generation from python, hdl, fpga, hardware-design

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