make
This skill guides you through building maintainable Makefiles for C/C++ using phony targets, pattern rules, and automatic dependency tracking. Learn to structure multi-file projects, manage compiler flags, diagnose rebuild issues, and convert ad-hoc compile commands into robust build systems.
make helps you write and debug Makefiles for C/C++ projects using pattern rules, dependency tracking, and idiomatic build patterns.
AI-generated summary based on this skill's SKILL.md
Decision gist · record as of 2026-06-27
make helps you write and debug Makefiles for C/C++ projects using pattern rules, dependency tracking, and idiomatic build patterns. This skill guides you through building maintainable Makefiles for C/C++ using phony targets, pattern rules, and automatic dependency tracking. Learn to structure multi-file projects, manage compiler flags, diagnose rebuild issues, and convert ad-hoc compile commands into robust build systems.
Use it when
- make provides automatic variables to simplify rule writing.
- make supports automatic dependency generation to detect when header files change.
Verify before relying
Read SKILL.md below before installing (2 files). Open directory: indexed for reading, not audited.
Install
mohitmishra786/low-level-dev-skills/make · repository language: JavaScript
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Frequently asked questions
AI-generated answers based on this skill's SKILL.md and metadata
How do I write a Makefile for a C project?
make is a build automation tool that compiles C/C++ projects by defining rules and dependencies. Start by listing your source files, object files, and the final executable. Use pattern rules like `%.o: %.c` to compile each `.c` file to `.o`, and link them together. Define variables for `CC`, `CFLAGS`, and `LDFLAGS` to keep commands consistent. Always mark non-file targets (like `clean`, `all`) as `.PHONY` to prevent conflicts with actual files. A minimal Makefile includes a main target, object file rules, and a clean rule.
What do the special variables $@, $<, and $^ mean in make?
make provides automatic variables to simplify rule writing. `$@` expands to the target filename, `$<` expands to the first prerequisite, and `$^` expands to all prerequisites (space-separated). For example, in `program: main.o util.o`, the rule `$(CC) $^ -o $@` becomes `gcc main.o util.o -o program`. These variables eliminate repetition and make pattern rules work correctly across different targets.
How can I add automatic dependency tracking to my Makefile?
make supports automatic dependency generation to detect when header files change. Use `gcc -MM` to generate `.d` dependency files listing which headers each `.c` file includes. Add a rule like `%.d: %.c` that runs `$(CC) -MM $< > $@`, then include those files with `-include *.d` at the end of your Makefile. This ensures rebuilds trigger when any included header changes, eliminating the "header change not detected" problem.
Why does my Makefile rebuild everything every time I run it?
make rebuilds when prerequisites are missing or newer than targets. Common causes: missing dependency files (use automatic dependency generation), phony targets not marked `.PHONY` (causing false rebuilds), or timestamps corrupted by version control. Verify your pattern rules use `$@`, `$<`, and `$^` correctly. Check that `.PHONY` declarations appear before their rules. If headers aren't tracked, implement automatic dependency generation with `gcc -MM` and `-include *.d`.
What does the 'missing separator' error mean and how do I fix it?
make requires recipe lines (commands under rules) to start with a literal tab character, not spaces. The error "missing separator" signals you used spaces instead. In your editor, ensure tab insertion is enabled when editing Makefiles. Most editors have a setting to show whitespace or force tabs in Makefile mode. If copying from documentation, re-type the indentation manually. This is a frequent source of frustration but easily fixed by checking your editor's tab/space settings.
How do I organize a multi-directory C project with make?
make supports multi-directory projects through recursive make or flat structures. For recursive make, create a Makefile in each subdirectory and call them from a top-level Makefile using `$(MAKE) -C subdir`. For flat structures, use vpath or explicit paths like `src/%.o: src/%.c` to locate sources. Flat Makefiles scale better and avoid re-invocation overhead. Define `VPATH` or use pattern rules with directory prefixes to locate source and object files consistently across your project tree.
SKILL.md
Rendered from the published skill. Quoted content, verbatim.
GNU Make
Purpose
Guide agents through idiomatic Makefile patterns for C/C++ projects: phony targets, pattern rules, automatic dependency generation, and common build idioms.
Triggers
- "How do I write a Makefile for my C project?"
- "My Makefile rebuilds everything every time"
- "How do I add dependency tracking to Make?"
- "What does
$@,$<,$^mean?" - "I'm getting 'make: Nothing to be done for all'"
- "How do I convert my shell compile script to a Makefile?"
Workflow
1. Minimal correct Makefile for C
```makefile CC := gcc CFLAGS := -std=c11 -Wall -Wextra -g -O2 LDFLAGS := LDLIBS :=
SRCS := $(wildcard src/*.c) OBJS := $(SRCS:src/%.c=build/%.o) TARGET := build/prog
.PHONY: all clean
all:
(truncated - see the full file via the links below)
File tree — 2 files
skills/build-systems/make/SKILL.md
skills/build-systems/make/references/cheatsheet.md
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