{"categories":[{"label":"Build Tools","url":"https://skillfed.io/packages/category/software-development-build-tools/6"}],"enrichment":{"capability":"Parses SystemVerilog modules and exposes their parameters, ports, and connections as SQL-queryable DataFrames for analysis and extraction.","skillfed_tags":["hardware-design","rtl-analysis","sql-query"],"use_cases":["Extract all parameters with default values from a module to understand its configuration points.","Query input or output ports by direction to document or validate a module's interface.","Identify which parameters have been overridden in a specific instantiation versus left at defaults.","Automate RTL documentation by querying port widths, types, and connectivity across modules.","Build design verification scripts that programmatically inspect module structure without parsing SystemVerilog by hand."],"what_it_does":"svql is a Python tool that parses SystemVerilog module files and makes their structural information\u2014parameters, ports, and connections\u2014queryable via SQL. It wraps the pyslang parser to extract module metadata and stores it in pandas DataFrames, then uses pandasql to let you write SQL SELECT queries against those tables. The typical workflow is to load a .sv file, call module.query() with a SQL statement, and get back a DataFrame of results.\n\nThis is useful for hardware engineers and design automation workflows where you need to inspect or extract specific details from RTL modules without manually reading the source. The aging maintenance status and lack of recent activity suggest the project is stable but not actively developed; it works well for its narrow purpose but may not receive updates for new SystemVerilog standards or edge cases.","worth_installing":"Yes, if you work with SystemVerilog and need to query module structure programmatically. Install friction is low and the license is permissive. However, the aging maintenance status means you should verify that pyslang handles your specific SystemVerilog dialect and features before committing to it in a critical workflow; no vulnerabilities are known, but don't expect rapid fixes if issues arise."},"id":"svql","links":{"html":"https://skillfed.io/packages/svql","md":"https://skillfed.io/packages/svql.md","pypi":"https://pypi.org/project/svql/"},"maintenance":{"status":"aging"},"meta":{"latest_release":"2025-03-06","license_spdx":null,"license_treatment":"permissive","name":"svql","python_support":"supports_current","summary":"Query SystemVerilog modules with SQL."},"popularity":{"monthly_downloads":76905,"position":14580,"tier":"top_15000"},"security":{"n_vulnerabilities":0},"version":"0.1.9"}