{"categories":[{"label":"Documentation","url":"https://skillfed.io/packages/category/software-development-documentation"},{"label":"Electronic Design Automation (EDA)","url":"https://skillfed.io/packages/category/scientific-engineering-electronic-design-automation-eda"}],"enrichment":{"capability":"Generates UVM (Universal Verification Methodology) register models in SystemVerilog from compiled SystemRDL register descriptions, enabling automated hardware verification testbench creation.","skillfed_tags":["hardware-verification","register-generation","systemverilog"],"use_cases":["Generate UVM register models from SystemRDL specifications in a CI/CD pipeline to keep testbenches synchronized with register changes.","Automate register abstraction layer creation for complex SoCs with hundreds of registers across multiple address maps.","Customize generated UVM classes via user-defined templates to match project-specific verification patterns or naming conventions.","Export register models as includable headers for integration into existing UVM testbenches without package namespace constraints.","Enable reuse of register class definitions across multiple design instances to reduce generated code size and compilation time."],"what_it_does":"PeakRDL-uvm is a code generator that converts compiled SystemRDL register specifications into ready-to-use UVM register models in SystemVerilog. It sits downstream of the systemrdl-compiler, taking an elaborated register tree and emitting either a SystemVerilog package or header file containing UVM register classes, fields, and memories that mirror the original register layout. The tool supports optional features like UVM factory integration, class definition reuse, and user-defined template overrides via jinja2.\n\nIt is primarily used as a plugin to the PeakRDL command-line tool, though it can also be invoked directly from Python code. The generated UVM models are meant to accelerate hardware verification by automating the creation of the register abstraction layer\u2014a tedious and error-prone task when done by hand\u2014allowing verification engineers to focus on testbench logic rather than register boilerplate.","worth_installing":"Yes, if you work with SystemRDL-based hardware designs and need UVM testbenches. The package is stable (Production/Stable classifier), has no known vulnerabilities, and low install friction. The copyleft license is a consideration for proprietary flows\u2014verify compliance before use. Aging maintenance (262 days since last release) is typical for mature tools but means slower response to new UVM or SystemVerilog standards."},"id":"peakrdl-uvm","links":{"html":"https://skillfed.io/packages/peakrdl-uvm","md":"https://skillfed.io/packages/peakrdl-uvm.md","pypi":"https://pypi.org/project/peakrdl-uvm/"},"maintenance":{"status":"aging"},"meta":{"latest_release":"2025-11-25","license_spdx":null,"license_treatment":"copyleft","name":"peakrdl-uvm","python_support":"supports_current","summary":"Generate UVM register model from compiled SystemRDL input"},"popularity":{"monthly_downloads":160007,"position":10681,"tier":"top_15000"},"security":{"n_vulnerabilities":0},"version":"2.4.0"}